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/linux-6.12.1/Documentation/devicetree/bindings/interrupt-controller/
Dmti,gic.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/mti,gic.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Paul Burton <paulburton@kernel.org>
11 - Thomas Bogendoerfer <tsbogend@alpha.franken.de>
15 It also supports local (per-processor) interrupts and software-generated
16 interrupts which can be used as IPIs. The GIC also includes a free-running
17 global timer, per-CPU count/compare timers, and a watchdog.
23 "#interrupt-cells":
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/linux-6.12.1/Documentation/devicetree/bindings/powerpc/
Dibm,powerpc-cpu-features.txt3 (skiboot/doc/device-tree/ibm,powerpc-cpu-features/binding.txt)
9 ibm,powerpc-cpu-features binding
12 This device tree binding describes CPU features available to software, with
19 /cpus/ibm,powerpc-cpu-features node binding
20 -------------------------------------------
22 Node: ibm,powerpc-cpu-features
24 Description: Container of CPU feature nodes.
26 The node name must be "ibm,powerpc-cpu-features".
35 - compatible
38 Definition: "ibm,powerpc-cpu-features"
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/linux-6.12.1/arch/xtensa/
DKconfig1 # SPDX-License-Identifier: GPL-2.0
61 Xtensa processors are 32-bit RISC machines designed by Tensilica
66 a home page at <http://www.linux-xtensa.org/>.
105 def_bool $(success,test "$(shell,echo __XTENSA_EB__ | $(CC) -E -P -)" = 1)
111 …def_bool $(success,test "$(shell,echo __XTENSA_CALL0_ABI__ | $(CC) -mabi=call0 -E -P - 2>/dev/null…
120 bool "fsf - default (not generic) configuration"
124 bool "dc232b - Diamond 232L Standard Core Rev.B (LE)"
131 bool "dc233c - Diamond 233L Standard Core Rev.C (LE)"
167 ie: it supports a TLB with auto-loading, page protection.
224 byte and 2-byte access to memory attached to instruction bus.
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/linux-6.12.1/drivers/irqchip/
Dirq-mips-gic.c6 * Copyright (C) 2008 Ralf Baechle (ralf@linux-mips.org)
7 * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved.
10 #define pr_fmt(fmt) "irq-mips-gic: " fmt
26 #include <asm/mips-cps.h>
30 #include <dt-bindings/interrupt-controller/mips-gic.h>
35 /* Add 2 to convert GIC CPU pin to core interrupt */
44 #define GIC_HWIRQ_TO_LOCAL(x) ((x) - GIC_LOCAL_HWIRQ_BASE)
47 #define GIC_HWIRQ_TO_SHARED(x) ((x) - GIC_SHARED_HWIRQ_BASE)
105 irq -= GIC_PIN_TO_VEC_OFFSET; in gic_bind_eic_interrupt()
111 static void gic_send_ipi(struct irq_data *d, unsigned int cpu) in gic_send_ipi() argument
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/linux-6.12.1/arch/xtensa/include/asm/
Dmmu_context.h8 * Copyright (C) 2001 - 2013 Tensilica Inc.
23 #include <asm/vectors.h>
27 #include <asm-generic/mm_hooks.h>
28 #include <asm-generic/percpu.h>
35 #define cpu_asid_cache(cpu) per_cpu(asid_cache, cpu) argument
39 * any user or kernel context. We use the reserved values in the
44 * 2 reserved
45 * 3 reserved
51 #define ASID_MASK ((1 << XCHAL_MMU_ASID_BITS) - 1)
70 static inline void get_new_mmu_context(struct mm_struct *mm, unsigned int cpu) in get_new_mmu_context() argument
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/linux-6.12.1/arch/m68k/
DKconfig.machine1 # SPDX-License-Identifier: GPL-2.0
23 This option enables support for the 68000-based Atari series of
41 browse the documentation available at <http://www.mac.linux-m68k.org/>;
50 Say Y here if you want to run Linux on an MC680x0-based Apollo
70 build a kernel which can run on MVME147 single-board computers. If
130 The Q40 is a Motorola 68040-based successor to the Sinclair QL
133 Q60. Select your CPU below. For 68LC060 don't forget to enable FPU
212 Disable the CPU internal registers protection in user mode,
306 Support for the Sysam AMCORE open-hardware generic board.
312 Support for the Sysam stmark2 open-hardware generic board.
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/linux-6.12.1/kernel/irq/
Dmatrix.c1 // SPDX-License-Identifier: GPL-2.0
8 #include <linux/cpu.h>
41 * irq_alloc_matrix - Allocate a irq_matrix structure and initialize it
51 unsigned int cpu, matrix_size = BITS_TO_LONGS(matrix_bits); in irq_alloc_matrix() local
58 m->system_map = &m->scratch_map[matrix_size]; in irq_alloc_matrix()
60 m->matrix_bits = matrix_bits; in irq_alloc_matrix()
61 m->alloc_start = alloc_start; in irq_alloc_matrix()
62 m->alloc_end = alloc_end; in irq_alloc_matrix()
63 m->alloc_size = alloc_end - alloc_start; in irq_alloc_matrix()
64 m->maps = __alloc_percpu(struct_size(m->maps, alloc_map, matrix_size * 2), in irq_alloc_matrix()
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/linux-6.12.1/arch/x86/kernel/apic/
Dvector.c1 // SPDX-License-Identifier: GPL-2.0-only
30 unsigned int cpu; member
78 info->mask = mask; in init_irq_alloc_info()
94 while (irqd->parent_data) in apic_chip_data()
95 irqd = irqd->parent_data; in apic_chip_data()
97 return irqd->chip_data; in apic_chip_data()
104 return apicd ? &apicd->hw_irq_cfg : NULL; in irqd_cfg()
119 INIT_HLIST_NODE(&apicd->clist); in alloc_apic_chip_data()
129 unsigned int cpu) in apic_update_irq_cfg() argument
135 apicd->hw_irq_cfg.vector = vector; in apic_update_irq_cfg()
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/linux-6.12.1/arch/arm64/kernel/
Dhead.S1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Low-level CPU initialisation
6 * Copyright (C) 1994-2002 Russell King
7 * Copyright (C) 2003-2012 ARM Ltd.
21 #include <asm/asm-offsets.h>
27 #include <asm/kernel-pgtable.h>
30 #include <asm/pgtable-hwdef.h>
38 #include "efi-header.S"
46 * ---------------------------
49 * MMU = off, D-cache = off, I-cache = on or off,
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Dproton-pack.c1 // SPDX-License-Identifier: GPL-2.0-only
6 * https://developer.arm.com/support/arm-security-updates/speculative-processor-vulnerability
12 * Copyright (C) 2018 ARM Ltd, All Rights Reserved.
20 #include <linux/arm-smccc.h>
22 #include <linux/cpu.h>
28 #include <asm/debug-monitors.h>
32 #include <asm/vectors.h>
37 * onlining a late CPU.
70 * This one sucks. A CPU is either:
72 * - Mitigated in hardware and advertised by ID_AA64PFR0_EL1.CSV2.
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Dentry.S1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Low-level exception handling code
10 #include <linux/arm-smccc.h>
16 #include <asm/asm-offsets.h>
29 #include <asm/asm-uaccess.h>
44 * skipped by the trampoline vectors, to trigger the cleanup.
64 sub x0, sp, x0 // x0' = sp' - x0 = (sp + x0) - x0 = sp
66 sub x0, sp, x0 // x0'' = sp' - x0' = (sp + x0) - sp = x0
67 sub sp, sp, x0 // sp'' = sp' - x0 = (sp + x0) - x0 = sp
89 * after panic() re-enables interrupts.
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/linux-6.12.1/Documentation/filesystems/xfs/
Dxfs-delayed-logging-design.rst1 .. SPDX-License-Identifier: GPL-2.0
33 details logged are made up of the changes to in-core structures rather than
34 on-disk structures. Other objects - typically buffers - have their physical
40 The reason for these differences is to keep the amount of log space and CPU time
64 place. This means that permanent transactions can be used for one-shot
65 modifications, but one-shot reservations cannot be used for permanent
68 In the code, a one-shot transaction pattern looks somewhat like this::
97 While this might look similar to a one-shot transaction, there is an important
123 the on-disk journal.
165 transaction, we have to reserve enough space to record a full leaf-to-root split
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/linux-6.12.1/arch/arc/kernel/
Dentry-arcv2.S1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * ARCv2 ISA based core Low Level Intr/Traps/Exceptions(non-TLB) Handling
17 ; first 16 lines are reserved for exceptions and are not configurable.
20 .cpu HS
29 # Initial 16 slots are Exception Vectors
44 VECTOR reserved ; Reserved slots
45 VECTOR reserved ; Reserved slots
47 # Begin Interrupt Vectors
58 .rept NR_CPU_IRQS - 8
64 reserved: label
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/linux-6.12.1/Documentation/arch/arm/
Dmemory.rst13 The ARM CPU is capable of addressing a maximum of 4GB virtual memory
30 ffff1000 ffff7fff Reserved.
33 ffff0000 ffff0fff CPU vector page.
34 The CPU vectors are mapped here if the
35 CPU supports vector relocation (control
39 in proc-xscale.S to flush the whole data
43 DTCM mounted inside the CPU.
46 ITCM mounted inside the CPU.
53 ff800000 ffbfffff Permanent, fixed read-only mapping of the
59 VMALLOC_START VMALLOC_END-1 vmalloc() / ioremap() space.
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/linux-6.12.1/arch/x86/include/asm/
Dsegment.h1 /* SPDX-License-Identifier: GPL-2.0 */
14 ((((base) & _AC(0xff000000,ULL)) << (56-24)) | \
16 (((limit) & _AC(0x000f0000,ULL)) << (48-16)) | \
61 * The layout of the per-CPU GDT under Linux:
63 * 0 - null <=== cacheline #1
64 * 1 - reserved
65 * 2 - reserved
66 * 3 - reserved
68 * 4 - unused <=== cacheline #2
69 * 5 - unused
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/linux-6.12.1/drivers/infiniband/hw/efa/
Defa_main.c1 // SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
3 * Copyright 2018-2024 Amazon.com, Inc. or its affiliates. All rights reserved.
50 ibdev_err(&dev->ibdev, in unimplemented_aenq_handler()
58 atomic64_inc(&dev->stats.keep_alive_rcvd); in efa_keep_alive()
70 struct pci_dev *pdev = dev->pdev; in efa_release_bars()
79 u16 cqn = eqe->u.comp_event.cqn; in efa_process_comp_eqe()
83 cq = xa_load(&dev->cqs_xa, cqn); in efa_process_comp_eqe()
85 ibdev_err_ratelimited(&dev->ibdev, in efa_process_comp_eqe()
86 "Completion event on non-existent CQ[%u]", in efa_process_comp_eqe()
91 cq->ibcq.comp_handler(&cq->ibcq, cq->ibcq.cq_context); in efa_process_comp_eqe()
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/linux-6.12.1/arch/powerpc/kernel/
Dhead_book3s_32.S1 /* SPDX-License-Identifier: GPL-2.0-or-later */
4 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
9 * Low-level exception handlers and MMU support
14 * This file contains the low-level support and setup for the
30 #include <asm/asm-offsets.h>
34 #include <asm/feature-fixups.h>
40 /* see the comment for clear_bats() -- Cort */ \
65 * -- Cort
77 * pointer (r1) points to just below the end of the half-meg region
78 * from 0x380000 - 0x400000, which is mapped in already.
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Dprom.c1 // SPDX-License-Identifier: GPL-2.0-or-later
6 * Copyright (C) 1996-2005 Paul Mackerras.
31 #include <linux/cpu.h>
49 #include <asm/pci-bridge.h>
94 * overlaps_initrd - check for overlap with page aligned extension of
111 * move_device_tree - move tree to an unused area, if needed.
122 DBG("-> move_device_tree\n"); in move_device_tree()
128 !memblock_is_memory(start + size - 1) || in move_device_tree()
139 DBG("<- move_device_tree\n"); in move_device_tree()
143 * ibm,pa/pi-features is a per-cpu property that contains a string of
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Dhead_64.S1 /* SPDX-License-Identifier: GPL-2.0-or-later */
4 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
9 * Low-level exception handlers and MMU support
16 * This file contains the entry point for the 64-bit kernel along
17 * with some early initialization code common to all 64-bit powerpc
28 #include <asm/head-64.h>
29 #include <asm/asm-offsets.h>
42 #include <asm/ppc-opcode.h>
43 #include <asm/feature-fixups.h>
45 #include <asm/exception-64s.h>
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/linux-6.12.1/fs/xfs/
Dxfs_log_priv.h1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2000-2003,2005 Silicon Graphics, Inc.
4 * All Rights Reserved.
74 * By covering, we mean changing the h_tail_lsn in the last on-disk
75 * log write such that no allocation transactions will be re-done during
76 * recovery after a system crash. Recovery starts at the last on-disk
80 * space allocation transactions which can undo non-transactional changes
93 * non-dummy transaction. The first dummy changes the h_tail_lsn to
102 * IDLE -- no logging has been done on the file system or
104 * NEED -- logging has occurred and we need a dummy transaction
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/linux-6.12.1/arch/arm64/kvm/hyp/include/nvhe/
Dfixed_config.h1 /* SPDX-License-Identifier: GPL-2.0-only */
26 * - Needed by common Linux distributions (e.g., floating point)
27 * - Trivial to support, e.g., supporting the feature does not introduce or
29 * - Cannot be trapped or prevent the guest from using anyway
34 * - Floating-point and Advanced SIMD
35 * - Data Independent Timing
36 * - Spectre/Meltdown Mitigation
48 * - AArch64 guests only (no support for AArch32 guests):
51 * - RAS (v1)
64 * - Branch Target Identification
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/linux-6.12.1/drivers/net/ethernet/intel/fm10k/
Dfm10k_main.c1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 2013 - 2019 Intel Corporation. */
18 "Copyright(c) 2013 - 2019 Intel Corporation.";
27 * fm10k_init_module - Driver Registration Routine
43 return -ENOMEM; in fm10k_init_module()
58 * fm10k_exit_module - Driver Exit Cleanup Routine
77 struct page *page = bi->page; in fm10k_alloc_mapped_page()
87 rx_ring->rx_stats.alloc_failed++; in fm10k_alloc_mapped_page()
92 dma = dma_map_page(rx_ring->dev, page, 0, PAGE_SIZE, DMA_FROM_DEVICE); in fm10k_alloc_mapped_page()
97 if (dma_mapping_error(rx_ring->dev, dma)) { in fm10k_alloc_mapped_page()
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/linux-6.12.1/arch/powerpc/include/asm/
Dreg.h1 /* SPDX-License-Identifier: GPL-2.0 */
6 * number used in the Programming Environments Manual For 32-Bit
17 #include <asm/asm-const.h>
18 #include <asm/feature-fixups.h>
74 /* so tests for these bits fail on 32-bit */
116 #define MSR_TS_N 0 /* Non-transactional */
120 #define MSR_TM_RESV(x) (((x) & MSR_TS_MASK) == MSR_TS_MASK) /* Reserved */
161 /* Power Management - Processor Stop Status and Control Register Fields */
165 #define PSSCR_PSLL_MASK 0x000F0000 /* Power-Saving Level Limit */
169 #define PSSCR_PLS 0xf000000000000000 /* Power-saving Level Status */
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/linux-6.12.1/arch/powerpc/sysdev/
Dmpic.c9 * Copyright 2010-2012 Freescale Semiconductor, Inc.
152 #define MPIC_INFO(name) mpic->hw_set[MPIC_IDX_##name]
162 unsigned int cpu = 0; in mpic_processor_id() local
164 if (!(mpic->flags & MPIC_SECONDARY)) in mpic_processor_id()
165 cpu = hard_smp_processor_id(); in mpic_processor_id()
167 return cpu; in mpic_processor_id()
182 return dcr_read(rb->dhost, reg); in _mpic_read()
185 return in_be32(rb->base + (reg >> 2)); in _mpic_read()
188 return in_le32(rb->base + (reg >> 2)); in _mpic_read()
199 dcr_write(rb->dhost, reg, value); in _mpic_write()
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/linux-6.12.1/arch/arm/mach-sa1100/
Dgeneric.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * linux/arch/arm/mach-sa1100/generic.c
15 #include <linux/dma-mapping.h>
23 #include <linux/irqchip/irq-sa11x0.h>
67 unsigned int sa11x0_getspeed(unsigned int cpu) in sa11x0_getspeed() argument
69 if (cpu) in sa11x0_getspeed()
75 * Default power-off for SA1100
83 /* enable wake-up on GPIO0 (Assabet...) */ in sa1100_power_off()
102 /* Use on-chip reset capability */ in sa11x0_restart()
110 dev->dev.platform_data = data; in sa11x0_register_device()
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