Lines Matching +full:reserved +full:- +full:cpu +full:- +full:vectors
9 * Copyright 2010-2012 Freescale Semiconductor, Inc.
152 #define MPIC_INFO(name) mpic->hw_set[MPIC_IDX_##name]
162 unsigned int cpu = 0; in mpic_processor_id() local
164 if (!(mpic->flags & MPIC_SECONDARY)) in mpic_processor_id()
165 cpu = hard_smp_processor_id(); in mpic_processor_id()
167 return cpu; in mpic_processor_id()
182 return dcr_read(rb->dhost, reg); in _mpic_read()
185 return in_be32(rb->base + (reg >> 2)); in _mpic_read()
188 return in_le32(rb->base + (reg >> 2)); in _mpic_read()
199 dcr_write(rb->dhost, reg, value); in _mpic_write()
203 out_be32(rb->base + (reg >> 2), value); in _mpic_write()
207 out_le32(rb->base + (reg >> 2), value); in _mpic_write()
214 enum mpic_reg_type type = mpic->reg_type; in _mpic_ipi_read()
218 if ((mpic->flags & MPIC_BROKEN_IPI) && type == mpic_access_mmio_le) in _mpic_ipi_read()
220 return _mpic_read(type, &mpic->gregs, offset); in _mpic_ipi_read()
228 _mpic_write(mpic->reg_type, &mpic->gregs, offset, value); in _mpic_ipi_write()
242 return _mpic_read(mpic->reg_type, &mpic->tmregs, offset); in _mpic_tm_read()
250 _mpic_write(mpic->reg_type, &mpic->tmregs, offset, value); in _mpic_tm_write()
255 unsigned int cpu = mpic_processor_id(mpic); in _mpic_cpu_read() local
257 return _mpic_read(mpic->reg_type, &mpic->cpuregs[cpu], reg); in _mpic_cpu_read()
262 unsigned int cpu = mpic_processor_id(mpic); in _mpic_cpu_write() local
264 _mpic_write(mpic->reg_type, &mpic->cpuregs[cpu], reg, value); in _mpic_cpu_write()
269 unsigned int isu = src_no >> mpic->isu_shift; in _mpic_irq_read()
270 unsigned int idx = src_no & mpic->isu_mask; in _mpic_irq_read()
273 val = _mpic_read(mpic->reg_type, &mpic->isus[isu], in _mpic_irq_read()
278 mpic->isu_reg0_shadow[src_no]; in _mpic_irq_read()
286 unsigned int isu = src_no >> mpic->isu_shift; in _mpic_irq_write()
287 unsigned int idx = src_no & mpic->isu_mask; in _mpic_irq_write()
289 _mpic_write(mpic->reg_type, &mpic->isus[isu], in _mpic_irq_write()
294 mpic->isu_reg0_shadow[src_no] = in _mpic_irq_write()
299 #define mpic_read(b,r) _mpic_read(mpic->reg_type,&(b),(r))
300 #define mpic_write(b,r,v) _mpic_write(mpic->reg_type,&(b),(r),(v))
320 rb->base = ioremap(phys_addr + offset, size); in _mpic_map_mmio()
321 BUG_ON(rb->base == NULL); in _mpic_map_mmio()
328 phys_addr_t phys_addr = dcr_resource_start(mpic->node, 0); in _mpic_map_dcr()
329 rb->dhost = dcr_map(mpic->node, phys_addr + offset, size); in _mpic_map_dcr()
330 BUG_ON(!DCR_MAP_OK(rb->dhost)); in _mpic_map_dcr()
337 if (mpic->flags & MPIC_USES_DCR) in mpic_map()
355 mpic_write(mpic->gregs, MPIC_INFO(GREG_IPI_VECTOR_PRI_0), MPIC_VECPRI_MASK); in mpic_test_broken_ipi()
356 r = mpic_read(mpic->gregs, MPIC_INFO(GREG_IPI_VECTOR_PRI_0)); in mpic_test_broken_ipi()
360 mpic->flags |= MPIC_BROKEN_IPI; in mpic_test_broken_ipi()
371 if (source >= 128 || !mpic->fixups) in mpic_is_ht_interrupt()
373 return mpic->fixups[source].base != NULL; in mpic_is_ht_interrupt()
379 struct mpic_irq_fixup *fixup = &mpic->fixups[source]; in mpic_ht_end_irq()
381 if (fixup->applebase) { in mpic_ht_end_irq()
382 unsigned int soff = (fixup->index >> 3) & ~3; in mpic_ht_end_irq()
383 unsigned int mask = 1U << (fixup->index & 0x1f); in mpic_ht_end_irq()
384 writel(mask, fixup->applebase + soff); in mpic_ht_end_irq()
386 raw_spin_lock(&mpic->fixup_lock); in mpic_ht_end_irq()
387 writeb(0x11 + 2 * fixup->index, fixup->base + 2); in mpic_ht_end_irq()
388 writel(fixup->data, fixup->base + 4); in mpic_ht_end_irq()
389 raw_spin_unlock(&mpic->fixup_lock); in mpic_ht_end_irq()
396 struct mpic_irq_fixup *fixup = &mpic->fixups[source]; in mpic_startup_ht_interrupt()
400 if (fixup->base == NULL) in mpic_startup_ht_interrupt()
404 source, fixup->index); in mpic_startup_ht_interrupt()
405 raw_spin_lock_irqsave(&mpic->fixup_lock, flags); in mpic_startup_ht_interrupt()
407 writeb(0x10 + 2 * fixup->index, fixup->base + 2); in mpic_startup_ht_interrupt()
408 tmp = readl(fixup->base + 4); in mpic_startup_ht_interrupt()
412 writel(tmp, fixup->base + 4); in mpic_startup_ht_interrupt()
413 raw_spin_unlock_irqrestore(&mpic->fixup_lock, flags); in mpic_startup_ht_interrupt()
418 mpic->save_data[source].fixup_data = tmp | 1; in mpic_startup_ht_interrupt()
424 struct mpic_irq_fixup *fixup = &mpic->fixups[source]; in mpic_shutdown_ht_interrupt()
428 if (fixup->base == NULL) in mpic_shutdown_ht_interrupt()
434 raw_spin_lock_irqsave(&mpic->fixup_lock, flags); in mpic_shutdown_ht_interrupt()
435 writeb(0x10 + 2 * fixup->index, fixup->base + 2); in mpic_shutdown_ht_interrupt()
436 tmp = readl(fixup->base + 4); in mpic_shutdown_ht_interrupt()
438 writel(tmp, fixup->base + 4); in mpic_shutdown_ht_interrupt()
439 raw_spin_unlock_irqrestore(&mpic->fixup_lock, flags); in mpic_shutdown_ht_interrupt()
444 mpic->save_data[source].fixup_data = tmp & ~1; in mpic_shutdown_ht_interrupt()
477 printk(KERN_DEBUG "mpic: - HT:%02x.%x %s MSI mapping found @ 0x%llx\n", in mpic_scan_ht_msi()
516 printk(KERN_INFO "mpic: - HT:%02x.%x [0x%02x] vendor %04x device %04x" in mpic_scan_ht_pic()
528 mpic->fixups[irq].index = i; in mpic_scan_ht_pic()
529 mpic->fixups[irq].base = base; in mpic_scan_ht_pic()
530 /* Apple HT PIC has a non-standard way of doing EOIs */ in mpic_scan_ht_pic()
532 mpic->fixups[irq].applebase = devbase + 0x60; in mpic_scan_ht_pic()
534 mpic->fixups[irq].applebase = NULL; in mpic_scan_ht_pic()
536 mpic->fixups[irq].data = readl(base + 4) | 0x80000000; in mpic_scan_ht_pic()
549 mpic->fixups = kcalloc(128, sizeof(*mpic->fixups), GFP_KERNEL); in mpic_scan_ht_pics()
550 BUG_ON(mpic->fixups == NULL); in mpic_scan_ht_pics()
553 raw_spin_lock_init(&mpic->fixup_lock); in mpic_scan_ht_pics()
555 /* Map U3 config space. We assume all IO-APICs are on the primary bus in mpic_scan_ht_pics()
616 return (src >= mpic->ipi_vecs[0] && src <= mpic->ipi_vecs[3]); in mpic_is_ipi()
622 return (src >= mpic->timer_vecs[0] && src <= mpic->timer_vecs[7]); in mpic_is_tm()
625 /* Convert a cpu mask from logical to physical cpu numbers. */
673 DBG("%p: %s: enable_irq: %d (src %d)\n", mpic, mpic->name, d->irq, src); in mpic_unmask_irq()
680 if (!loops--) { in mpic_unmask_irq()
694 DBG("%s: disable_irq: %d (src %d)\n", mpic->name, d->irq, src); in mpic_mask_irq()
702 if (!loops--) { in mpic_mask_irq()
715 DBG("%s: end_irq: %d\n", mpic->name, d->irq); in mpic_end_irq()
764 DBG("%s: end_irq: %d\n", mpic->name, d->irq); in mpic_end_ht_irq()
782 unsigned int src = virq_to_hw(d->irq) - mpic->ipi_vecs[0]; in mpic_unmask_ipi()
784 DBG("%s: enable_ipi: %d (ipi %d)\n", mpic->name, d->irq, src); in mpic_unmask_ipi()
800 * applying to them. We EOI them late to avoid re-entering. in mpic_end_ipi()
810 unsigned int src = virq_to_hw(d->irq) - mpic->timer_vecs[0]; in mpic_unmask_tm()
812 DBG("%s: enable_tm: %d (tm %d)\n", mpic->name, d->irq, src); in mpic_unmask_tm()
820 unsigned int src = virq_to_hw(d->irq) - mpic->timer_vecs[0]; in mpic_mask_tm()
832 if (mpic->flags & MPIC_SINGLE_DEST_CPU) { in mpic_set_affinity()
876 mpic, d->irq, src, flow_type); in mpic_set_irq_type()
878 if (src >= mpic->num_sources) in mpic_set_irq_type()
879 return -EINVAL; in mpic_set_irq_type()
938 if (src >= mpic->num_sources) in mpic_set_vector()
955 if (src >= mpic->num_sources) in mpic_set_destination()
1005 struct mpic *mpic = h->host_data; in mpic_host_map()
1010 if (hw == mpic->spurious_vec) in mpic_host_map()
1011 return -EINVAL; in mpic_host_map()
1012 if (mpic->protected && test_bit(hw, mpic->protected)) { in mpic_host_map()
1015 return -EPERM; in mpic_host_map()
1019 else if (hw >= mpic->ipi_vecs[0]) { in mpic_host_map()
1020 WARN_ON(mpic->flags & MPIC_SECONDARY); in mpic_host_map()
1024 irq_set_chip_and_handler(virq, &mpic->hc_ipi, in mpic_host_map()
1030 if (hw >= mpic->timer_vecs[0] && hw <= mpic->timer_vecs[7]) { in mpic_host_map()
1031 WARN_ON(mpic->flags & MPIC_SECONDARY); in mpic_host_map()
1035 irq_set_chip_and_handler(virq, &mpic->hc_tm, in mpic_host_map()
1043 if (hw >= mpic->num_sources) { in mpic_host_map()
1046 return -EINVAL; in mpic_host_map()
1052 chip = &mpic->hc_irq; in mpic_host_map()
1057 chip = &mpic->hc_ht_irq; in mpic_host_map()
1068 /* If the MPIC was reset, then all vectors have already been in mpic_host_map()
1072 if (!mpic_is_ipi(mpic, hw) && (mpic->flags & MPIC_NO_RESET)) { in mpic_host_map()
1073 int cpu; in mpic_host_map() local
1076 cpu = mpic_processor_id(mpic); in mpic_host_map()
1080 mpic_set_destination(virq, cpu); in mpic_host_map()
1092 struct mpic *mpic = h->host_data; in mpic_host_xlate()
1101 if (intsize >= 4 && (mpic->flags & MPIC_FSL)) { in mpic_host_xlate()
1105 * an "interrupt type". Fourth is type-specific data. in mpic_host_xlate()
1113 if (!(mpic->flags & MPIC_FSL_HAS_EIMR)) in mpic_host_xlate()
1116 if (intspec[3] >= ARRAY_SIZE(mpic->err_int_vecs)) in mpic_host_xlate()
1117 return -EINVAL; in mpic_host_xlate()
1119 *out_hwirq = mpic->err_int_vecs[intspec[3]]; in mpic_host_xlate()
1123 if (intspec[0] >= ARRAY_SIZE(mpic->ipi_vecs)) in mpic_host_xlate()
1124 return -EINVAL; in mpic_host_xlate()
1126 *out_hwirq = mpic->ipi_vecs[intspec[0]]; in mpic_host_xlate()
1129 if (intspec[0] >= ARRAY_SIZE(mpic->timer_vecs)) in mpic_host_xlate()
1130 return -EINVAL; in mpic_host_xlate()
1132 *out_hwirq = mpic->timer_vecs[intspec[0]]; in mpic_host_xlate()
1137 return -EINVAL; in mpic_host_xlate()
1173 BUG_ON(!(mpic->flags & MPIC_SECONDARY)); in mpic_cascade()
1179 chip->irq_eoi(&desc->irq_data); in mpic_cascade()
1192 if (!(mpic->flags & MPIC_FSL)) in fsl_mpic_get_version()
1195 brr1 = _mpic_read(mpic->reg_type, &mpic->thiscpuregs, in fsl_mpic_get_version()
1232 { .type = "open-pic", }, in mpic_alloc()
1233 { .compatible = "open-pic", }, in mpic_alloc()
1238 * If we were not passed a device-tree node, then perform the default in mpic_alloc()
1251 /* Check if it is DCR-based */ in mpic_alloc()
1252 if (of_property_read_bool(node, "dcr-reg")) { in mpic_alloc()
1262 /* Read extra device-tree properties into the flags variable */ in mpic_alloc()
1263 if (of_property_read_bool(node, "big-endian")) in mpic_alloc()
1265 if (of_property_read_bool(node, "pic-no-reset")) in mpic_alloc()
1267 if (of_property_read_bool(node, "single-cpu-affinity")) in mpic_alloc()
1279 mpic->name = name; in mpic_alloc()
1280 mpic->node = node; in mpic_alloc()
1281 mpic->paddr = phys_addr; in mpic_alloc()
1282 mpic->flags = flags; in mpic_alloc()
1284 mpic->hc_irq = mpic_irq_chip; in mpic_alloc()
1285 mpic->hc_irq.name = name; in mpic_alloc()
1286 if (!(mpic->flags & MPIC_SECONDARY)) in mpic_alloc()
1287 mpic->hc_irq.irq_set_affinity = mpic_set_affinity; in mpic_alloc()
1289 mpic->hc_ht_irq = mpic_irq_ht_chip; in mpic_alloc()
1290 mpic->hc_ht_irq.name = name; in mpic_alloc()
1291 if (!(mpic->flags & MPIC_SECONDARY)) in mpic_alloc()
1292 mpic->hc_ht_irq.irq_set_affinity = mpic_set_affinity; in mpic_alloc()
1296 mpic->hc_ipi = mpic_ipi_chip; in mpic_alloc()
1297 mpic->hc_ipi.name = name; in mpic_alloc()
1300 mpic->hc_tm = mpic_tm_chip; in mpic_alloc()
1301 mpic->hc_tm.name = name; in mpic_alloc()
1303 mpic->num_sources = 0; /* so far */ in mpic_alloc()
1305 if (mpic->flags & MPIC_LARGE_VECTORS) in mpic_alloc()
1310 mpic->timer_vecs[0] = intvec_top - 12; in mpic_alloc()
1311 mpic->timer_vecs[1] = intvec_top - 11; in mpic_alloc()
1312 mpic->timer_vecs[2] = intvec_top - 10; in mpic_alloc()
1313 mpic->timer_vecs[3] = intvec_top - 9; in mpic_alloc()
1314 mpic->timer_vecs[4] = intvec_top - 8; in mpic_alloc()
1315 mpic->timer_vecs[5] = intvec_top - 7; in mpic_alloc()
1316 mpic->timer_vecs[6] = intvec_top - 6; in mpic_alloc()
1317 mpic->timer_vecs[7] = intvec_top - 5; in mpic_alloc()
1318 mpic->ipi_vecs[0] = intvec_top - 4; in mpic_alloc()
1319 mpic->ipi_vecs[1] = intvec_top - 3; in mpic_alloc()
1320 mpic->ipi_vecs[2] = intvec_top - 2; in mpic_alloc()
1321 mpic->ipi_vecs[3] = intvec_top - 1; in mpic_alloc()
1322 mpic->spurious_vec = intvec_top; in mpic_alloc()
1325 psrc = of_get_property(mpic->node, "protected-sources", &psize); in mpic_alloc()
1328 mpic->protected = bitmap_zalloc(intvec_top + 1, GFP_KERNEL); in mpic_alloc()
1329 BUG_ON(mpic->protected == NULL); in mpic_alloc()
1333 __set_bit(psrc[i], mpic->protected); in mpic_alloc()
1338 mpic->hw_set = mpic_infos[MPIC_GET_REGSET(mpic->flags)]; in mpic_alloc()
1342 if (mpic->flags & MPIC_BIG_ENDIAN) in mpic_alloc()
1343 mpic->reg_type = mpic_access_mmio_be; in mpic_alloc()
1345 mpic->reg_type = mpic_access_mmio_le; in mpic_alloc()
1348 * An MPIC with a "dcr-reg" property must be accessed that way, but in mpic_alloc()
1352 if (mpic->flags & MPIC_USES_DCR) in mpic_alloc()
1353 mpic->reg_type = mpic_access_dcr; in mpic_alloc()
1355 BUG_ON(mpic->flags & MPIC_USES_DCR); in mpic_alloc()
1359 mpic_map(mpic, mpic->paddr, &mpic->gregs, MPIC_INFO(GREG_BASE), 0x1000); in mpic_alloc()
1360 mpic_map(mpic, mpic->paddr, &mpic->tmregs, MPIC_INFO(TIMER_BASE), 0x1000); in mpic_alloc()
1362 if (mpic->flags & MPIC_FSL) { in mpic_alloc()
1367 * magic per-cpu area -- and they don't even show up in the in mpic_alloc()
1368 * non-magic per-cpu copies that this driver normally uses. in mpic_alloc()
1370 mpic_map(mpic, mpic->paddr, &mpic->thiscpuregs, in mpic_alloc()
1380 * interrupt vectors. This space is stolen from the in mpic_alloc()
1384 * Available vector space = intvec_top - 13, where 13 in mpic_alloc()
1385 * is the number of vectors which have been consumed by in mpic_alloc()
1389 ret = mpic_setup_error_int(mpic, intvec_top - 13); in mpic_alloc()
1398 * platforms that don't know the MPIC version at compile-time, in mpic_alloc()
1399 * such as qemu-e500, turn off coreint if this MPIC doesn't in mpic_alloc()
1414 /* When using a device-node, reset requests are only honored if the MPIC in mpic_alloc()
1417 if (!(mpic->flags & MPIC_NO_RESET)) { in mpic_alloc()
1419 mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0), in mpic_alloc()
1420 mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0)) in mpic_alloc()
1422 while( mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0)) in mpic_alloc()
1428 if (mpic->flags & MPIC_ENABLE_COREINT) in mpic_alloc()
1429 mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0), in mpic_alloc()
1430 mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0)) in mpic_alloc()
1433 if (mpic->flags & MPIC_ENABLE_MCK) in mpic_alloc()
1434 mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0), in mpic_alloc()
1435 mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0)) in mpic_alloc()
1444 /* Map the per-CPU registers */ in mpic_alloc()
1446 unsigned int cpu = get_hard_smp_processor_id(i); in mpic_alloc() local
1448 mpic_map(mpic, mpic->paddr, &mpic->cpuregs[cpu], in mpic_alloc()
1449 MPIC_INFO(CPU_BASE) + cpu * MPIC_INFO(CPU_STRIDE), in mpic_alloc()
1454 * Read feature register. For non-ISU MPICs, num sources as well. On in mpic_alloc()
1457 greg_feature = mpic_read(mpic->gregs, MPIC_INFO(GREG_FEATURE_0)); in mpic_alloc()
1461 * device-tree and board support code can override it on buggy hw. in mpic_alloc()
1462 * If we get passed an isu_size (multi-isu MPIC) then we use that in mpic_alloc()
1468 last_irq = isu_size * MPIC_MAX_ISU - 1; in mpic_alloc()
1469 of_property_read_u32(mpic->node, "last-interrupt-source", &last_irq); in mpic_alloc()
1471 last_irq = irq_count - 1; in mpic_alloc()
1476 mpic->num_sources = isu_size; in mpic_alloc()
1477 mpic_map(mpic, mpic->paddr, &mpic->isus[0], in mpic_alloc()
1482 mpic->isu_size = isu_size; in mpic_alloc()
1483 mpic->isu_shift = 1 + __ilog2(mpic->isu_size - 1); in mpic_alloc()
1484 mpic->isu_mask = (1 << mpic->isu_shift) - 1; in mpic_alloc()
1486 mpic->irqhost = irq_domain_add_linear(mpic->node, in mpic_alloc()
1494 if (mpic->irqhost == NULL) in mpic_alloc()
1514 name, vers, (unsigned long long)mpic->paddr, num_possible_cpus()); in mpic_alloc()
1516 mpic->isu_size, mpic->isu_shift, mpic->isu_mask); in mpic_alloc()
1518 mpic->next = mpics; in mpic_alloc()
1521 if (!(mpic->flags & MPIC_SECONDARY)) { in mpic_alloc()
1523 irq_set_default_host(mpic->irqhost); in mpic_alloc()
1536 unsigned int isu_first = isu_num * mpic->isu_size; in mpic_assign_isu()
1541 paddr, &mpic->isus[isu_num], 0, in mpic_assign_isu()
1542 MPIC_INFO(IRQ_STRIDE) * mpic->isu_size); in mpic_assign_isu()
1544 if ((isu_first + mpic->isu_size) > mpic->num_sources) in mpic_assign_isu()
1545 mpic->num_sources = isu_first + mpic->isu_size; in mpic_assign_isu()
1550 int i, cpu; in mpic_init() local
1553 BUG_ON(mpic->num_sources == 0); in mpic_init()
1555 printk(KERN_INFO "mpic: Initializing for %d sources\n", mpic->num_sources); in mpic_init()
1560 if (mpic->flags & MPIC_FSL) { in mpic_init()
1573 /* Initialize timers to our reserved vectors and mask them for now */ in mpic_init()
1577 mpic_write(mpic->tmregs, in mpic_init()
1580 mpic_write(mpic->tmregs, in mpic_init()
1584 (mpic->timer_vecs[0] + i)); in mpic_init()
1587 /* Initialize IPIs to our reserved vectors and mark them disabled for now */ in mpic_init()
1593 (mpic->ipi_vecs[0] + i)); in mpic_init()
1597 DBG("MPIC flags: %x\n", mpic->flags); in mpic_init()
1598 if ((mpic->flags & MPIC_U3_HT_IRQS) && !(mpic->flags & MPIC_SECONDARY)) { in mpic_init()
1605 cpu = mpic_processor_id(mpic); in mpic_init()
1607 if (!(mpic->flags & MPIC_NO_RESET)) { in mpic_init()
1608 for (i = 0; i < mpic->num_sources; i++) { in mpic_init()
1614 if (mpic->protected && test_bit(i, mpic->protected)) in mpic_init()
1618 mpic_irq_write(i, MPIC_INFO(IRQ_DESTINATION), 1 << cpu); in mpic_init()
1623 mpic_write(mpic->gregs, MPIC_INFO(GREG_SPURIOUS), mpic->spurious_vec); in mpic_init()
1626 if (!(mpic->flags & MPIC_NO_PTHROU_DIS)) in mpic_init()
1627 mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0), in mpic_init()
1628 mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0)) in mpic_init()
1631 if (mpic->flags & MPIC_NO_BIAS) in mpic_init()
1632 mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0), in mpic_init()
1633 mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0)) in mpic_init()
1641 mpic->save_data = kmalloc_array(mpic->num_sources, in mpic_init()
1642 sizeof(*mpic->save_data), in mpic_init()
1644 BUG_ON(mpic->save_data == NULL); in mpic_init()
1648 if (mpic->flags & MPIC_SECONDARY) { in mpic_init()
1649 int virq = irq_of_parse_and_map(mpic->node, 0); in mpic_init()
1652 mpic->node, virq); in mpic_init()
1659 if (mpic->flags & MPIC_FSL_HAS_EIMR) in mpic_init()
1675 reg = mpic_ipi_read(src - mpic->ipi_vecs[0]) & in mpic_irq_set_priority()
1677 mpic_ipi_write(src - mpic->ipi_vecs[0], in mpic_irq_set_priority()
1680 reg = mpic_tm_read(src - mpic->timer_vecs[0]) & in mpic_irq_set_priority()
1682 mpic_tm_write(src - mpic->timer_vecs[0], in mpic_irq_set_priority()
1703 DBG("%s: setup_this_cpu(%d)\n", mpic->name, hard_smp_processor_id()); in mpic_setup_this_cpu()
1712 if (distribute_irqs && !(mpic->flags & MPIC_SINGLE_DEST_CPU)) { in mpic_setup_this_cpu()
1713 for (i = 0; i < mpic->num_sources ; i++) in mpic_setup_this_cpu()
1749 DBG("%s: teardown_this_cpu(%d)\n", mpic->name, hard_smp_processor_id()); in mpic_teardown_this_cpu()
1753 for (i = 0; i < mpic->num_sources ; i++) in mpic_teardown_this_cpu()
1774 DBG("%s: get_one_irq(reg 0x%x): %d\n", mpic->name, reg, src); in _mpic_get_one_irq()
1776 if (unlikely(src == mpic->spurious_vec)) { in _mpic_get_one_irq()
1777 if (mpic->flags & MPIC_SPV_EOI) in _mpic_get_one_irq()
1781 if (unlikely(mpic->protected && test_bit(src, mpic->protected))) { in _mpic_get_one_irq()
1783 mpic->name, (int)src); in _mpic_get_one_irq()
1788 return irq_linear_revmap(mpic->irqhost, src); in _mpic_get_one_irq()
1815 if (unlikely(src == mpic->spurious_vec)) { in mpic_get_coreint_irq()
1816 if (mpic->flags & MPIC_SPV_EOI) in mpic_get_coreint_irq()
1820 if (unlikely(mpic->protected && test_bit(src, mpic->protected))) { in mpic_get_coreint_irq()
1822 mpic->name, (int)src); in mpic_get_coreint_irq()
1826 return irq_linear_revmap(mpic->irqhost, src); in mpic_get_coreint_irq()
1851 unsigned int vipi = irq_create_mapping(mpic->irqhost, in mpic_request_ipis()
1852 mpic->ipi_vecs[0] + i); in mpic_request_ipis()
1861 void smp_mpic_message_pass(int cpu, int msg) in smp_mpic_message_pass() argument
1876 DBG("%s: send_ipi(ipi_no: %d)\n", mpic->name, msg); in smp_mpic_message_pass()
1879 physmask = 1 << get_hard_smp_processor_id(cpu); in smp_mpic_message_pass()
1899 void smp_mpic_setup_cpu(int cpu) in smp_mpic_setup_cpu() argument
1904 void mpic_reset_core(int cpu) in mpic_reset_core() argument
1908 int cpuid = get_hard_smp_processor_id(cpu); in mpic_reset_core()
1912 pir = mpic_read(mpic->gregs, MPIC_INFO(GREG_PROCESSOR_INIT)); in mpic_reset_core()
1914 mpic_write(mpic->gregs, MPIC_INFO(GREG_PROCESSOR_INIT), pir); in mpic_reset_core()
1915 mpic_read(mpic->gregs, MPIC_INFO(GREG_PROCESSOR_INIT)); in mpic_reset_core()
1919 mpic_write(mpic->gregs, MPIC_INFO(GREG_PROCESSOR_INIT), pir); in mpic_reset_core()
1920 mpic_read(mpic->gregs, MPIC_INFO(GREG_PROCESSOR_INIT)); in mpic_reset_core()
1924 if (mpic->flags & MPIC_FSL) { in mpic_reset_core()
1926 _mpic_write(mpic->reg_type, &mpic->cpuregs[cpuid], in mpic_reset_core()
1938 for (i = 0; i < mpic->num_sources; i++) { in mpic_suspend_one()
1939 mpic->save_data[i].vecprio = in mpic_suspend_one()
1941 mpic->save_data[i].dest = in mpic_suspend_one()
1952 mpic = mpic->next; in mpic_suspend()
1962 for (i = 0; i < mpic->num_sources; i++) { in mpic_resume_one()
1964 mpic->save_data[i].vecprio); in mpic_resume_one()
1966 mpic->save_data[i].dest); in mpic_resume_one()
1969 if (mpic->fixups) { in mpic_resume_one()
1970 struct mpic_irq_fixup *fixup = &mpic->fixups[i]; in mpic_resume_one()
1972 if (fixup->base) { in mpic_resume_one()
1974 if ((mpic->save_data[i].fixup_data & 1) == 0) in mpic_resume_one()
1978 writeb(0x10 + 2 * fixup->index, fixup->base + 2); in mpic_resume_one()
1980 writel(mpic->save_data[i].fixup_data & ~1, in mpic_resume_one()
1981 fixup->base + 4); in mpic_resume_one()
1994 mpic = mpic->next; in mpic_resume()