Lines Matching +full:reserved +full:- +full:cpu +full:- +full:vectors
1 # SPDX-License-Identifier: GPL-2.0
61 Xtensa processors are 32-bit RISC machines designed by Tensilica
66 a home page at <http://www.linux-xtensa.org/>.
105 def_bool $(success,test "$(shell,echo __XTENSA_EB__ | $(CC) -E -P -)" = 1)
111 …def_bool $(success,test "$(shell,echo __XTENSA_CALL0_ABI__ | $(CC) -mabi=call0 -E -P - 2>/dev/null…
120 bool "fsf - default (not generic) configuration"
124 bool "dc232b - Diamond 232L Standard Core Rev.B (LE)"
131 bool "dc233c - Diamond 233L Standard Core Rev.C (LE)"
167 ie: it supports a TLB with auto-loading, page protection.
224 byte and 2-byte access to memory attached to instruction bus.
231 This option is used to indicate that the system-on-a-chip (SOC)
233 the CPU core definition and currently needs to be selected manually.
245 bool "Enable Symmetric multi-processing support"
249 Enabled SMP Software; allows more than one CPU/CORE
254 int "Maximum number of CPUs (2-32)"
259 bool "Enable CPU hotplug support"
263 controlled through /sys/devices/system/cpu.
265 Say N if you want to disable CPU hotplug.
387 On some platforms (XT2000, for example), the CPU clock rate can
413 XT2000 is the name of Tensilica's feature-rich emulation platform.
435 int "CPU clock rate [MHz]"
442 The BogoMIPS value can easily be derived from the CPU frequency.
454 architectures, you should supply some command-line options at build
501 tristate "Host file-based simulated block device support"
510 int "Number of host file-based simulated block devices"
533 Another simulated disk in a host file for a buildroot-independent
558 bool "Use 8-bit access to XTFPGA LCD"
562 LCD may be connected with 4- or 8-bit interface, 8-bit access may
563 only be used with 8-bit interface. Please consult prototyping user
579 This unfortunately won't work for U-Boot and likely also won't
585 xt-gdb can't place a Software Breakpoint in the 0XD region prior
593 Selecting this will cause U-Boot to set the KERNEL Load and Entry
599 bool "Kernel Execute-In-Place from ROM"
602 Execute-In-Place allows the kernel to run from non-volatile storage
603 directly addressable by the CPU, such as NOR flash. This saves RAM
605 to RAM. Read-write sections, such as the data section and stack,
626 region: bits 0..3 -- for addresses 0x00000000..0x1fffffff,
627 bits 4..7 -- for addresses 0x20000000..0x3fffffff, and so on.
642 3: special (c and e are illegal, f is reserved).
646 2: WB, no-write-allocate cache,
657 Unpacked kernel image (including vectors) must be located completely
686 prompt "Relocatable vectors location"
689 Choose whether relocatable vectors are merged into the kernel .text
691 configurations without VECBASE register where vectors are always
692 placed at their hardware-defined locations.
695 bool "Merge relocatable vectors into kernel text"
698 This option puts relocatable vectors into the kernel .text section
703 bool "Put relocatable vectors at fixed address"
705 This option puts relocatable vectors at specific virtual address.
706 Vectors are merged with the .init data in the kernel image and
708 Use it to put vectors into IRAM or out of FLASH on kernels with
709 XIP-aware MTD support.
714 hex "Kernel vectors virtual address"
718 This is the virtual address of the (relocatable) vectors base.