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/linux-6.12.1/drivers/scsi/isci/
Dremote_node_context.h7 * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
20 * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
26 * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
61 * the remote node context in the silicon. It exists to model and manage
62 * the remote node context in the silicon.
100 * @SCI_RNC_INVALIDATING: transition state that will post an RNC invalidate to
104 * @SCI_RNC_RESUMING: transition state that will post an RNC resume to the
148 RNC_DEST_SUSPENDED, /* Set when suspend during post/invalidate */
155 * struct sci_remote_node_context - This structure contains the data
158 * the silicon RNC.
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/linux-6.12.1/arch/powerpc/boot/dts/fsl/
Dt1042si-post.dtsi2 * T1042 Silicon/SoC Device Tree Source (post include)
35 #include "t1040si-post.dtsi"
Dt2080si-post.dtsi2 * T2080 Silicon/SoC Device Tree Source (post include)
35 /include/ "t2081si-post.dtsi"
38 /include/ "qoriq-sata2-0.dtsi"
40 fsl,iommu-parent = <&pamu1>;
41 fsl,liodn-reg = <&guts 0x550>; /* SATA1LIODNR */
44 /include/ "qoriq-sata2-1.dtsi"
46 fsl,iommu-parent = <&pamu1>;
47 fsl,liodn-reg = <&guts 0x554>; /* SATA2LIODNR */
54 #address-cells = <2>;
55 #size-cells = <2>;
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Db4420si-post.dtsi2 * B4420 Silicon/SoC Device Tree Source (post include)
35 /include/ "b4si-post.dtsi"
39 compatible = "fsl,b4420-pcie", "fsl,qoriq-pcie-v2.4";
43 dcsr-epu@0 {
44 compatible = "fsl,b4420-dcsr-epu", "fsl,dcsr-epu";
46 dcsr-npc {
47 compatible = "fsl,b4420-dcsr-cnpc", "fsl,dcsr-cnpc";
49 dcsr-dpaa@9000 {
50 compatible = "fsl,b4420-dcsr-dpaa", "fsl,dcsr-dpaa";
52 dcsr-ocn@11000 {
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Dt1024si-post.dtsi2 * T1024 Silicon/SoC Device Tree Source (post include)
35 #include "t1023si-post.dtsi"
44 #address-cells = <1>;
45 #size-cells = <1>;
50 fsl,qe-num-riscs = <1>;
51 fsl,qe-num-snums = <28>;
52 brg-frequency = <0>;
53 bus-frequency = <0>;
59 compatible = "fsl,t1024-diu", "fsl,diu";
66 qeic: interrupt-controller@80 {
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Dmpc8641si-post.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * MPC8641 Silicon/SoC Device Tree Source (post include)
5 * Copyright 2016 Elettra-Sincrotrone Trieste S.C.p.A.
9 #address-cells = <2>;
10 #size-cells = <1>;
11 compatible = "fsl,mpc8641-localbus", "simple-bus";
16 #address-cells = <1>;
17 #size-cells = <1>;
19 compatible = "fsl,mpc8641-soc", "simple-bus";
20 bus-frequency = <0>;
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Dmpc8548si-post.dtsi2 * MPC8548 Silicon/SoC Device Tree Source (post include)
36 #address-cells = <2>;
37 #size-cells = <1>;
38 compatible = "fsl,mpc8548-lbc", "fsl,pq3-localbus", "simple-bus";
44 compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci";
47 bus-range = <0 0xff>;
48 #interrupt-cells = <1>;
49 #size-cells = <2>;
50 #address-cells = <3>;
55 compatible = "fsl,mpc8540-pci";
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Dc293si-post.dtsi2 * C293 Silicon/SoC Device Tree Source (post include)
36 #address-cells = <2>;
37 #size-cells = <1>;
44 compatible = "fsl,qoriq-pcie-v2.2", "fsl,qoriq-pcie";
46 #size-cells = <2>;
47 #address-cells = <3>;
48 bus-range = <0 255>;
49 clock-frequency = <33333333>;
54 #interrupt-cells = <1>;
55 #size-cells = <2>;
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Dbsc9131si-post.dtsi2 * BSC9131 Silicon/SoC Device Tree Source (post include)
4 * Copyright 2011-2012 Freescale Semiconductor Inc.
36 #address-cells = <2>;
37 #size-cells = <1>;
43 #address-cells = <1>;
44 #size-cells = <1>;
46 compatible = "fsl,bsc9131-immr", "simple-bus";
47 bus-frequency = <0>; // Filled out by uboot.
49 ecm-law@0 {
50 compatible = "fsl,ecm-law";
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Db4860si-post.dtsi2 * B4860 Silicon/SoC Device Tree Source (post include)
4 * Copyright 2012 - 2015 Freescale Semiconductor Inc.
35 /include/ "b4si-post.dtsi"
39 compatible = "fsl,b4860-pcie", "fsl,qoriq-pcie-v2.4";
45 #address-cells = <2>;
46 #size-cells = <2>;
47 fsl,iommu-parent = <&pamu0>;
51 #address-cells = <2>;
52 #size-cells = <2>;
53 cell-index = <1>;
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Dbsc9132si-post.dtsi2 * BSC9132 Silicon/SoC Device Tree Source (post include)
36 #address-cells = <2>;
37 #size-cells = <1>;
45 compatible = "fsl,bsc9132-pcie", "fsl,qoriq-pcie-v2.2";
47 #size-cells = <2>;
48 #address-cells = <3>;
49 bus-range = <0 255>;
54 #interrupt-cells = <1>;
55 #size-cells = <2>;
56 #address-cells = <3>;
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Dp1020si-post.dtsi2 * P1020/P1011 Silicon/SoC Device Tree Source (post include)
36 #address-cells = <2>;
37 #size-cells = <1>;
38 compatible = "fsl,p1020-elbc", "fsl,elbc", "simple-bus";
45 compatible = "fsl,mpc8548-pcie";
47 #size-cells = <2>;
48 #address-cells = <3>;
49 bus-range = <0 255>;
50 clock-frequency = <33333333>;
55 #interrupt-cells = <1>;
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Dp1010si-post.dtsi2 * P1010/P1014 Silicon/SoC Device Tree Source (post include)
36 #address-cells = <2>;
37 #size-cells = <1>;
44 compatible = "fsl,p1010-pcie", "fsl,qoriq-pcie-v2.3";
46 #size-cells = <2>;
47 #address-cells = <3>;
48 bus-range = <0 255>;
49 clock-frequency = <33333333>;
54 #interrupt-cells = <1>;
55 #size-cells = <2>;
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Dmpc8572si-post.dtsi2 * MPC8572 Silicon/SoC Device Tree Source (post include)
36 #address-cells = <2>;
37 #size-cells = <1>;
38 compatible = "fsl,mpc8572-elbc", "fsl,elbc", "simple-bus";
44 compatible = "fsl,mpc8548-pcie";
46 #size-cells = <2>;
47 #address-cells = <3>;
48 bus-range = <0 255>;
49 clock-frequency = <33333333>;
54 #interrupt-cells = <1>;
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Dmpc8544si-post.dtsi2 * MPC8544 Silicon/SoC Device Tree Source (post include)
36 #address-cells = <2>;
37 #size-cells = <1>;
38 compatible = "fsl,mpc8544-lbc", "fsl,pq3-localbus", "simple-bus";
44 compatible = "fsl,mpc8540-pci";
47 bus-range = <0 0xff>;
48 #interrupt-cells = <1>;
49 #size-cells = <2>;
50 #address-cells = <3>;
55 compatible = "fsl,mpc8548-pcie";
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Dp2020si-post.dtsi2 * P2020/P2010 Silicon/SoC Device Tree Source (post include)
36 #address-cells = <2>;
37 #size-cells = <1>;
38 compatible = "fsl,p2020-elbc", "fsl,elbc", "simple-bus";
44 compatible = "fsl,mpc8548-pcie";
46 #size-cells = <2>;
47 #address-cells = <3>;
48 bus-range = <0 255>;
49 clock-frequency = <33333333>;
55 #interrupt-cells = <1>;
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Dp1021si-post.dtsi2 * P1021/P1012 Silicon/SoC Device Tree Source (post include)
4 * Copyright 2011-2012 Freescale Semiconductor Inc.
36 #address-cells = <2>;
37 #size-cells = <1>;
38 compatible = "fsl,p1021-elbc", "fsl,elbc", "simple-bus";
45 compatible = "fsl,mpc8548-pcie";
47 #size-cells = <2>;
48 #address-cells = <3>;
49 bus-range = <0 255>;
50 clock-frequency = <33333333>;
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Dp1022si-post.dtsi2 * P1022/P1013 Silicon/SoC Device Tree Source (post include)
36 #address-cells = <2>;
37 #size-cells = <1>;
39 * The localbus on the P1022 is not a simple-bus because of the eLBC
42 compatible = "fsl,p1022-elbc", "fsl,elbc";
49 compatible = "fsl,mpc8548-pcie";
51 #size-cells = <2>;
52 #address-cells = <3>;
53 bus-range = <0 255>;
54 clock-frequency = <33333333>;
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Dmpc8568si-post.dtsi2 * MPC8568 Silicon/SoC Device Tree Source (post include)
36 #address-cells = <2>;
37 #size-cells = <1>;
38 compatible = "fsl,mpc8568-localbus", "fsl,pq3-localbus", "simple-bus";
45 compatible = "fsl,mpc8540-pci";
48 bus-range = <0 0xff>;
49 #interrupt-cells = <1>;
50 #size-cells = <2>;
51 #address-cells = <3>;
57 compatible = "fsl,mpc8548-pcie";
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Dmpc8536si-post.dtsi2 * MPC8536 Silicon/SoC Device Tree Source (post include)
36 #address-cells = <2>;
37 #size-cells = <1>;
38 compatible = "fsl,mpc8536-elbc", "fsl,elbc", "simple-bus";
44 compatible = "fsl,mpc8540-pci";
47 bus-range = <0 0xff>;
48 #interrupt-cells = <1>;
49 #size-cells = <2>;
50 #address-cells = <3>;
55 compatible = "fsl,mpc8548-pcie";
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Dmpc8569si-post.dtsi2 * MPC8569 Silicon/SoC Device Tree Source (post include)
36 #address-cells = <2>;
37 #size-cells = <1>;
38 compatible = "fsl,mpc8569-elbc", "fsl,elbc", "simple-bus";
45 compatible = "fsl,mpc8548-pcie";
47 #size-cells = <2>;
48 #address-cells = <3>;
49 bus-range = <0 255>;
50 clock-frequency = <33333333>;
56 #interrupt-cells = <1>;
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/linux-6.12.1/include/uapi/linux/
Dmii.h1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
3 * linux/mii.h: definitions for MII-compatible transceivers
23 #define MII_CTRL1000 0x09 /* 1000BASE-T control */
24 #define MII_STAT1000 0x0a /* 1000BASE-T status */
30 #define MII_NWAYTEST 0x14 /* N-way auto-neg test reg */
32 #define MII_SREVISION 0x16 /* Silicon revision */
55 #define BMSR_ERCAP 0x0001 /* Ext-reg capability */
58 #define BMSR_ANEGCAPABLE 0x0008 /* Able to do auto-negotiation */
60 #define BMSR_ANEGCOMPLETE 0x0020 /* Auto-negotiation complete */
63 #define BMSR_100HALF2 0x0200 /* Can do 100BASE-T2 HDX */
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/linux-6.12.1/drivers/media/tuners/
Dtda18271-priv.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 tda18271-priv.h - private header for the NXP TDA18271 silicon tuner
17 #include "tuner-i2c.h"
28 #define R_CPD 0x08 /* Cal Post-Divider byte */
32 #define R_MPD 0x0c /* Main Post-Divider byte */
62 /*---------------------------------------------------------------------*/
121 /*---------------------------------------------------------------------*/
162 /*---------------------------------------------------------------------*/
196 /*---------------------------------------------------------------------*/
/linux-6.12.1/drivers/net/ethernet/emulex/benet/
Dbe_hw.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright (C) 2005-2016 Broadcom.
7 * linux-drivers@emulex.com
16 * The software must write this register twice to post any command. First,
33 #define SLIPORT_SEMAPHORE_OFFSET_SH 0x94 /* PCI-CFG offset */
42 /* MPU semphore POST stage values */
44 #define POST_STAGE_HOST_RDY 0x2 /* Host has given go-ahed to FW */
46 #define POST_STAGE_ARMFW_RDY 0xc000 /* FW is done with POST */
127 #define DB_EQ_RING_ID_MASK 0x1FF /* bits 0 - 8 */
128 #define DB_EQ_RING_ID_EXT_MASK 0x3e00 /* bits 9-13 */
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/linux-6.12.1/drivers/infiniband/hw/hfi1/
Dpcie.c1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
3 * Copyright(c) 2015 - 2019 Intel Corporation.
27 struct pci_dev *pdev = dd->pcidev; in hfi1_pcie_init()
43 dd_dev_err(dd, "pci enable failed: error %d\n", -ret); in hfi1_pcie_init()
49 dd_dev_err(dd, "pci_request_regions fails: err %d\n", -ret); in hfi1_pcie_init()
53 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)); in hfi1_pcie_init()
60 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)); in hfi1_pcie_init()
90 * fields required to re-initialize after a chip reset, or for
111 return -EINVAL; in hfi1_pcie_ddinit()
114 dd->kregbase1 = ioremap(addr, RCV_ARRAY); in hfi1_pcie_ddinit()
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