dts/fsl/c293si-post.dtsi

2  * C293 Silicon/SoC Device Tree Source (post include)
36 	#address-cells = <2>;
37 	#size-cells = <1>;
44 	compatible = "fsl,qoriq-pcie-v2.2", "fsl,qoriq-pcie";
46 	#size-cells = <2>;
47 	#address-cells = <3>;
48 	bus-range = <0 255>;
49 	clock-frequency = <33333333>;
54 		#interrupt-cells = <1>;
55 		#size-cells = <2>;
56 		#address-cells = <3>;
59 		interrupt-map-mask = <0xf800 0 0 7>;
60 		interrupt-map = <
71 	#address-cells = <1>;
72 	#size-cells = <1>;
74 	compatible = "simple-bus";
75 	bus-frequency = <0>;		// Filled out by uboot.
77 	ecm-law@0 {
78 		compatible = "fsl,ecm-law";
80 		fsl,num-laws = <12>;
84 		compatible = "fsl,c293-ecm", "fsl,ecm";
89 	memory-controller@2000 {
90 		compatible = "fsl,c293-memory-controller";
95 /include/ "pq3-i2c-0.dtsi"
96 /include/ "pq3-i2c-1.dtsi"
97 /include/ "pq3-duart-0.dtsi"
98 /include/ "pq3-espi-0.dtsi"
100 		fsl,espi-num-chipselects = <1>;
103 /include/ "pq3-gpio-0.dtsi"
104 	L2: l2-cache-controller@20000 {
105 		compatible = "fsl,c293-l2-cache-controller";
107 		cache-line-size = <32>;	// 32 bytes
108 		cache-size = <0x80000>; // L2,512K
112 /include/ "pq3-dma-0.dtsi"
113 /include/ "pq3-esdhc-0.dtsi"
115 		compatible = "fsl,c293-esdhc", "fsl,esdhc";
116 		sdhci,auto-cmd12;
120 /include/ "qoriq-sec6.0-0.dtsi"
136 /include/ "qoriq-sec6.0-0.dtsi"
152 /include/ "qoriq-sec6.0-0.dtsi"
167 /include/ "pq3-mpic.dtsi"
168 /include/ "pq3-mpic-timer-B.dtsi"
170 /include/ "pq3-etsec2-0.dtsi"
172 		queue-group@b0000 {
177 /include/ "pq3-etsec2-1.dtsi"
179 		queue-group@b1000 {
184 	global-utilities@e0000 {
185 		compatible = "fsl,c293-guts";
187 		fsl,has-rstcr;