dts/fsl/mpc8548si-post.dtsi

2  * MPC8548 Silicon/SoC Device Tree Source (post include)
36 	#address-cells = <2>;
37 	#size-cells = <1>;
38 	compatible = "fsl,mpc8548-lbc", "fsl,pq3-localbus", "simple-bus";
44 	compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci";
47 	bus-range = <0 0xff>;
48 	#interrupt-cells = <1>;
49 	#size-cells = <2>;
50 	#address-cells = <3>;
55 	compatible = "fsl,mpc8540-pci";
58 	bus-range = <0 0xff>;
59 	#interrupt-cells = <1>;
60 	#size-cells = <2>;
61 	#address-cells = <3>;
66 	compatible = "fsl,mpc8548-pcie";
68 	#size-cells = <2>;
69 	#address-cells = <3>;
70 	bus-range = <0 255>;
71 	clock-frequency = <33333333>;
76 		#interrupt-cells = <1>;
77 		#size-cells = <2>;
78 		#address-cells = <3>;
81 		interrupt-map-mask = <0xf800 0 0 7>;
82 		interrupt-map = <
95 	#address-cells = <2>;
96 	#size-cells = <2>;
97 	fsl,srio-rmu-handle = <&rmu>;
101 		#address-cells = <2>;
102 		#size-cells = <2>;
103 		cell-index = <1>;
108 	#address-cells = <1>;
109 	#size-cells = <1>;
111 	compatible = "fsl,mpc8548-immr", "simple-bus";
112 	bus-frequency = <0>;		// Filled out by uboot.
114 	ecm-law@0 {
115 		compatible = "fsl,ecm-law";
117 		fsl,num-laws = <10>;
121 		compatible = "fsl,mpc8548-ecm", "fsl,ecm";
126 	memory-controller@2000 {
127 		compatible = "fsl,mpc8548-memory-controller";
132 /include/ "pq3-i2c-0.dtsi"
133 /include/ "pq3-i2c-1.dtsi"
134 /include/ "pq3-duart-0.dtsi"
136 	L2: l2-cache-controller@20000 {
137 		compatible = "fsl,mpc8548-l2-cache-controller";
139 		cache-line-size = <32>;	// 32 bytes
140 		cache-size = <0x80000>; // L2, 512K
144 /include/ "pq3-dma-0.dtsi"
145 /include/ "pq3-etsec1-0.dtsi"
146 /include/ "pq3-etsec1-1.dtsi"
147 /include/ "pq3-etsec1-2.dtsi"
148 /include/ "pq3-etsec1-3.dtsi"
150 /include/ "pq3-sec2.1-0.dtsi"
151 /include/ "pq3-mpic.dtsi"
152 /include/ "pq3-rmu-0.dtsi"
154 	global-utilities@e0000 {
155 		compatible = "fsl,mpc8548-guts";
157 		fsl,has-rstcr;
160 /include/ "pq3-power.dtsi"