dts/fsl/p2020si-post.dtsi

2  * P2020/P2010 Silicon/SoC Device Tree Source (post include)
36 	#address-cells = <2>;
37 	#size-cells = <1>;
38 	compatible = "fsl,p2020-elbc", "fsl,elbc", "simple-bus";
44 	compatible = "fsl,mpc8548-pcie";
46 	#size-cells = <2>;
47 	#address-cells = <3>;
48 	bus-range = <0 255>;
49 	clock-frequency = <33333333>;
55 		#interrupt-cells = <1>;
56 		#size-cells = <2>;
57 		#address-cells = <3>;
60 		interrupt-map-mask = <0xf800 0 0 7>;
61 		interrupt-map = <
73 	compatible = "fsl,mpc8548-pcie";
75 	#size-cells = <2>;
76 	#address-cells = <3>;
77 	bus-range = <0 255>;
78 	clock-frequency = <33333333>;
84 		#interrupt-cells = <1>;
85 		#size-cells = <2>;
86 		#address-cells = <3>;
89 		interrupt-map-mask = <0xf800 0 0 7>;
91 		interrupt-map = <
103 	compatible = "fsl,mpc8548-pcie";
105 	#size-cells = <2>;
106 	#address-cells = <3>;
107 	bus-range = <0 255>;
108 	clock-frequency = <33333333>;
114 		#interrupt-cells = <1>;
115 		#size-cells = <2>;
116 		#address-cells = <3>;
119 		interrupt-map-mask = <0xf800 0 0 7>;
121 		interrupt-map = <
132 	#address-cells = <1>;
133 	#size-cells = <1>;
135 	compatible = "fsl,p2020-immr", "simple-bus";
136 	bus-frequency = <0>;		// Filled out by uboot.
138 	ecm-law@0 {
139 		compatible = "fsl,ecm-law";
141 		fsl,num-laws = <12>;
145 		compatible = "fsl,p2020-ecm", "fsl,ecm";
150 	memory-controller@2000 {
151 		compatible = "fsl,p2020-memory-controller";
156 /include/ "pq3-i2c-0.dtsi"
157 /include/ "pq3-i2c-1.dtsi"
158 /include/ "pq3-duart-0.dtsi"
159 /include/ "pq3-espi-0.dtsi"
161 		fsl,espi-num-chipselects = <4>;
164 /include/ "pq3-dma-1.dtsi"
165 /include/ "pq3-gpio-0.dtsi"
167 	L2: l2-cache-controller@20000 {
168 		compatible = "fsl,p2020-l2-cache-controller";
170 		cache-line-size = <32>;	// 32 bytes
171 		cache-size = <0x80000>; // L2,512K
175 /include/ "pq3-dma-0.dtsi"
176 /include/ "pq3-usb2-dr-0.dtsi"
178 		compatible = "fsl-usb2-dr-v1.6", "fsl-usb2-dr";
180 /include/ "pq3-etsec1-0.dtsi"
182 		fsl,pmc-handle = <&etsec1_clk>;
185 /include/ "pq3-etsec1-timer-0.dtsi"
192 /include/ "pq3-etsec1-1.dtsi"
194 		fsl,pmc-handle = <&etsec2_clk>;
197 /include/ "pq3-etsec1-2.dtsi"
199 		fsl,pmc-handle = <&etsec3_clk>;
202 /include/ "pq3-esdhc-0.dtsi"
204 		compatible = "fsl,p2020-esdhc", "fsl,esdhc";
207 /include/ "pq3-sec3.1-0.dtsi"
208 /include/ "pq3-mpic.dtsi"
209 /include/ "pq3-mpic-timer-B.dtsi"
211 	global-utilities@e0000 {
212 		compatible = "fsl,p2020-guts";
214 		fsl,has-rstcr;
217 /include/ "pq3-power.dtsi"