| /linux-6.12.1/arch/mips/kernel/ |
| D | pm-cps.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
13 #include <asm/asm-offsets.h>
17 #include <asm/mips-cps.h>
20 #include <asm/pm-cps.h>
22 #include <asm/smp-cps.h>
26 * cps_nc_entry_fn - type of a generated non-coherent state entry function
28 * @nc_ready_count: pointer to a non-coherent mapping of the core ready_count
30 * The code entering & exiting non-coherent states is generated at runtime
33 * core-specific code particularly for cache routines. If coupled_coherence
34 * is non-zero and this is the entry function for the CPS_PM_NC_WAIT state,
[all …]
|
| D | cps-vec.S | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */
10 #include <asm/asm-offsets.h>
17 #include <asm/smp-cps.h>
51 * Set dest to non-zero if the core supports the MT ASE, else zero. If
66 * Set dest to non-zero if the core supports MIPSr6 multithreading
131 /* Skip core-level init if we started up coherent */
135 /* Perform any further required core-level initialisation */
140 * Boot any other VPEs within this core that should be online, and
195 /* Check that the core implements the MT ASE */
216 /* Retrieve the number of VPEs within the core */
[all …]
|
| /linux-6.12.1/tools/perf/pmu-events/arch/x86/amdzen5/ |
| D | l2-cache.json | 5 …"BriefDescription": "L2 cache requests of non-cacheable type (non-cached data and instructions rea…
65 "BriefDescription": "L2 cache requests: non-coherent, non-cacheable LS sized reads.",
71 "BriefDescription": "L2 cache requests: coherent, non-cacheable LS sized reads.",
83 …"BriefDescription": "Core to L2 cache requests (not including L2 prefetch) with status: instructio…
89 …"BriefDescription": "Core to L2 cache requests (not including L2 prefetch) with status: instructio…
95 …"BriefDescription": "Core to L2 cache requests (not including L2 prefetch) with status: instructio…
101 …"BriefDescription": "Core to L2 cache requests (not including L2 prefetch) for instruction cache h…
107 …"BriefDescription": "Core to L2 cache requests (not including L2 prefetch) for instruction cache a…
113 …"BriefDescription": "Core to L2 cache requests (not including L2 prefetch) with status: data cache…
119 …"BriefDescription": "Core to L2 cache requests (not including L2 prefetch) for data and instructio…
[all …]
|
| /linux-6.12.1/drivers/usb/host/ |
| D | octeon-hcd.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
11 * Copyright (c) 2003-2010 Cavium Networks (support@cavium.com). All rights
102 * Core AHB Configuration Register (GAHBCFG)
104 * This register can be used to configure the core after power-on or a change in
105 * mode of operation. This register mainly contains AHB system-related
107 * core. In general, software need not know about this interface except to
110 * The application must program this register as part of the O2P USB core
120 * Core Interrupt register (GINTSTS.PTxFEmp) is triggered. This
126 * @nptxfemplvl: Non-Periodic TxFIFO Empty Level (NPTxFEmpLvl)
128 * Indicates when the Non-Periodic TxFIFO Empty Interrupt bit in
[all …]
|
| /linux-6.12.1/tools/perf/pmu-events/arch/x86/broadwell/ |
| D | uncore-interconnect.json | 3 …"BriefDescription": "Number of entries allocated. Account for Any type: e.g. Snoop, Core aperture,…
12 …Core outgoing valid entries. Such entry is defined as valid from its allocation till first of IDI0…
21 … waiting for data return from memory controller. Account for coherent and non-coherent requests in…
31 …de. Such entry is defined as valid when it is allocated till data sent to Core (first chunk, IDI0)…
36 …de. Such entry is defined as valid when it is allocated till data sent to Core (first chunk, IDI0)…
41 …"BriefDescription": "Total number of Core outgoing entries allocated. Accounts for Coherent and no…
50 … "BriefDescription": "Number of Core coherent Data Read entries allocated in DirectData mode",
55 … "PublicDescription": "Number of Core coherent Data Read entries allocated in DirectData mode.",
60 …"BriefDescription": "Number of Writes allocated - any write transactions: full/partials writes and…
|
| /linux-6.12.1/tools/perf/pmu-events/arch/x86/amdzen3/ |
| D | cache.json | 5 …"BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache reads (including har…
11 "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache stores.",
17 "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache shared reads.",
23 "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Instruction cache reads.",
29 …"BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache state change request…
35 "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). PrefetchL2Cmd.",
41 …"BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). L2 Prefetcher. All prefetches a…
64 "BriefDescription": "All L2 Cache Requests (Breakdown 2 - Rare). Data cache read sized.",
70 …"BriefDescription": "All L2 Cache Requests (Breakdown 2 - Rare). Data cache read sized non-cacheab…
76 "BriefDescription": "All L2 Cache Requests (Breakdown 2 - Rare). Instruction cache read sized.",
[all …]
|
| /linux-6.12.1/tools/perf/pmu-events/arch/x86/tigerlake/ |
| D | other.json | 3 …"BriefDescription": "Core cycles where the core was running in a manner where Turbo may be clipped…
7 …Core cycles where the core was running with power-delivery for baseline license level 0. This inc…
12 …"BriefDescription": "Core cycles where the core was running in a manner where Turbo may be clipped…
16 …Core cycles where the core was running with power-delivery for license level 1. This includes hig…
21 …"BriefDescription": "Core cycles where the core was running in a manner where Turbo may be clipped…
25 …Core cycles where the core was running with power-delivery for license level 2 (introduced in Skyl…
|
| /linux-6.12.1/tools/perf/pmu-events/arch/x86/snowridgex/ |
| D | cache.json | 3 …"BriefDescription": "Counts the number of core requests (demand and L1 prefetchers) rejected by th…
7 …core requests rejected by the L2 queue (L2Q) due to a full or nearly full condition, which likely …
24 … The XQ may reject transactions from the L2Q (non-cacheable requests), BBL (L2 misses) and WOB (L…
28 … "BriefDescription": "Counts the total number of L2 Cache accesses. Counts on a per core basis.",
32 …ejects front door requests for CRd/DRd/RFO/ItoM/L2 Prefetches only. Counts on a per core basis.",
36 …ion": "Counts the number of L2 Cache accesses that resulted in a hit. Counts on a per core basis.",
40 …rom a front door request only (does not include rejects or recycles), Counts on a per core basis.",
45 …on": "Counts the number of L2 Cache accesses that resulted in a miss. Counts on a per core basis.",
49 …rom a front door request only (does not include rejects or recycles). Counts on a per core basis.",
54 …ts the number of L2 Cache accesses that miss the L2 and get rejected. Counts on a per core basis.",
[all …]
|
| /linux-6.12.1/tools/perf/pmu-events/arch/x86/elkhartlake/ |
| D | cache.json | 3 …"BriefDescription": "Counts the number of core requests (demand and L1 prefetchers) rejected by th…
7 …core requests rejected by the L2 queue (L2Q) due to a full or nearly full condition, which likely …
24 … The XQ may reject transactions from the L2Q (non-cacheable requests), BBL (L2 misses) and WOB (L…
28 … "BriefDescription": "Counts the total number of L2 Cache accesses. Counts on a per core basis.",
32 …ejects front door requests for CRd/DRd/RFO/ItoM/L2 Prefetches only. Counts on a per core basis.",
36 …ion": "Counts the number of L2 Cache accesses that resulted in a hit. Counts on a per core basis.",
40 …rom a front door request only (does not include rejects or recycles), Counts on a per core basis.",
45 …on": "Counts the number of L2 Cache accesses that resulted in a miss. Counts on a per core basis.",
49 …rom a front door request only (does not include rejects or recycles). Counts on a per core basis.",
54 …ts the number of L2 Cache accesses that miss the L2 and get rejected. Counts on a per core basis.",
[all …]
|
| /linux-6.12.1/Documentation/driver-api/ |
| D | xillybus.rst | 10 - Introduction
11 -- Background
12 -- Xillybus Overview
14 - Usage
15 -- User interface
16 -- Synchronization
17 -- Seekable pipes
19 - Internals
20 -- Source code organization
21 -- Pipe attributes
[all …]
|
| /linux-6.12.1/tools/perf/pmu-events/arch/x86/amdzen1/ |
| D | cache.json | 5 …etch windows transferred from IC pipe to DE instruction decoder (includes non-cacheable and cachea…
35 … instruction stream was being modified by another processor in an MP system - typically a highly u…
52 …l. IC pipe was stalled during this clock cycle (including IC to OC fetches) due to back-pressure.",
58 …ache lines invalidated. A non-SMC event is CMC (cross modifying code), either from the other threa…
64 …ache lines invalidated. A non-SMC event is CMC (cross modifying code), either from the other threa…
75 …"BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache reads (including har…
81 "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache stores.",
87 "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache shared reads.",
93 "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Instruction cache reads.",
99 …"BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache state change request…
[all …]
|
| /linux-6.12.1/tools/perf/pmu-events/arch/x86/alderlaken/ |
| D | cache.json | 3 …"Counts the number of cacheable memory requests that miss in the LLC. Counts on a per core basis.",
7 … HW prefetches. If the core has access to an L3 cache, the LLC is the L3 cache, otherwise it is th…
12 … "Counts the number of cacheable memory requests that access the LLC. Counts on a per core basis.",
16 … HW prefetches. If the core has access to an L3 cache, the LLC is the L3 cache, otherwise it is th…
21 … the number of cycles the core is stalled due to an instruction cache or TLB miss which hit in the…
25 …cycles the core is stalled due to an instruction cache or translation lookaside buffer (TLB) miss …
30 …"Counts the number of cycles the core is stalled due to an instruction cache or TLB miss which hit…
34 …er of cycles the core is stalled due to an instruction cache or translation lookaside buffer (TLB)…
39 …"BriefDescription": "Counts the number of cycles the core is stalled due to an instruction cache o…
43 …"PublicDescription": "Counts the number of cycles the core is stalled due to an instruction cache …
[all …]
|
| /linux-6.12.1/tools/perf/pmu-events/arch/x86/sandybridge/ |
| D | uncore-cache.json | 3 … "BriefDescription": "L3 Lookup any request that access cache and found line in E or S-state.",
12 "BriefDescription": "L3 Lookup any request that access cache and found line in I-state.",
21 "BriefDescription": "L3 Lookup any request that access cache and found line in M-state.",
30 "BriefDescription": "L3 Lookup any request that access cache and found line in MESI-state.",
39 …Description": "L3 Lookup external snoop request that access cache and found line in E or S-state.",
48 …BriefDescription": "L3 Lookup external snoop request that access cache and found line in I-state.",
57 …BriefDescription": "L3 Lookup external snoop request that access cache and found line in M-state.",
66 …efDescription": "L3 Lookup external snoop request that access cache and found line in MESI-state.",
75 … "BriefDescription": "L3 Lookup read request that access cache and found line in E or S-state.",
84 "BriefDescription": "L3 Lookup read request that access cache and found line in I-state.",
[all …]
|
| /linux-6.12.1/tools/perf/pmu-events/arch/x86/ivybridge/ |
| D | uncore-cache.json | 3 … "BriefDescription": "L3 Lookup any request that access cache and found line in E or S-state.",
12 "BriefDescription": "L3 Lookup any request that access cache and found line in I-state.",
21 "BriefDescription": "L3 Lookup any request that access cache and found line in M-state.",
30 "BriefDescription": "L3 Lookup any request that access cache and found line in MESI-state.",
39 …Description": "L3 Lookup external snoop request that access cache and found line in E or S-state.",
48 …BriefDescription": "L3 Lookup external snoop request that access cache and found line in I-state.",
57 …BriefDescription": "L3 Lookup external snoop request that access cache and found line in M-state.",
66 …efDescription": "L3 Lookup external snoop request that access cache and found line in MESI-state.",
75 … "BriefDescription": "L3 Lookup read request that access cache and found line in E or S-state.",
84 "BriefDescription": "L3 Lookup read request that access cache and found line in I-state.",
[all …]
|
| /linux-6.12.1/arch/arm/mach-omap2/ |
| D | omap-headsmp.S | 1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * Copyright (C) 2009-2014 Texas Instruments, Inc.
21 /* Physical address needed since MMU not enabled yet on secondary core */
38 * secondary core is held until we're ready for it to initialise.
39 * The primary core will update this flag using a hardware
58 .arch armv7-a
77 * secondary core is held until we're ready for it to initialise.
78 * The primary core will update this flag using a hardware
93 * should now contain the SVC stack for this core
113 * bit 1 == Non-Secure Enable
[all …]
|
| /linux-6.12.1/Documentation/hwmon/ |
| D | pmbus-core.rst | 2 PMBus core driver and internal API
9 power-management protocol with a fully defined command language that facilitates
11 protocol is implemented over the industry-standard SMBus serial interface and
12 enables programming, control, and real-time monitoring of compliant power
18 promoted by the PMBus Implementers Forum (PMBus-IF), comprising 30+ adopters
22 commands, and manufacturers can add as many non-standard commands as they like.
23 Also, different PMBUs devices act differently if non-supported commands are
29 device specific extensions in addition to the core PMBus driver, since it is
34 to modify the core PMBus driver repeatedly for new devices, the PMBus driver was
35 split into core, generic, and device specific code. The core code (in
[all …]
|
| /linux-6.12.1/tools/perf/pmu-events/arch/x86/haswell/ |
| D | uncore-cache.json | 3 … "BriefDescription": "L3 Lookup any request that access cache and found line in E or S-state.",
12 "BriefDescription": "L3 Lookup any request that access cache and found line in I-state.",
21 "BriefDescription": "L3 Lookup any request that access cache and found line in M-state.",
30 "BriefDescription": "L3 Lookup any request that access cache and found line in MESI-state.",
39 …Description": "L3 Lookup external snoop request that access cache and found line in E or S-state.",
48 …BriefDescription": "L3 Lookup external snoop request that access cache and found line in I-state.",
57 …BriefDescription": "L3 Lookup external snoop request that access cache and found line in M-state.",
66 …efDescription": "L3 Lookup external snoop request that access cache and found line in MESI-state.",
75 … "BriefDescription": "L3 Lookup read request that access cache and found line in E or S-state.",
84 "BriefDescription": "L3 Lookup read request that access cache and found line in I-state.",
[all …]
|
| D | uncore-interconnect.json | 13 …"BriefDescription": "Number of entries allocated. Account for Any type: e.g. Snoop, Core aperture,…
22 …Core outgoing valid entries. Such entry is defined as valid from its allocation till first of IDI0…
31 … waiting for data return from memory controller. Account for coherent and non-coherent requests in…
41 …"BriefDescription": "Total number of Core outgoing entries allocated. Accounts for Coherent and no…
50 …"BriefDescription": "Number of Writes allocated - any write transactions: full/partials writes and…
|
| /linux-6.12.1/drivers/cpuidle/ |
| D | cpuidle-cps.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
12 #include <asm/pm-cps.h>
17 STATE_NC_WAIT, /* MIPS wait instruction, non-coherent */
18 STATE_CLOCK_GATED, /* Core clock gated */
19 STATE_POWER_GATED, /* Core power gated */
30 * At least one core must remain powered up & clocked in order for the in cps_nc_enter()
33 * TODO: don't treat core 0 specially, just prevent the final core in cps_nc_enter()
36 if (cpus_are_siblings(0, dev->cpu) && (index > STATE_NC_WAIT)) in cps_nc_enter()
52 return -EINVAL; in cps_nc_enter()
57 return -EINTR; in cps_nc_enter()
[all …]
|
| /linux-6.12.1/drivers/nvdimm/ |
| D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
3 tristate "NVDIMM (Non-Volatile Memory Device) Support"
9 Generic support for non-volatile memory devices including
10 ACPI-6-NFIT defined resources. On platforms that define an
28 non-standard OEM-specific E820 memory type (type-12, see
31 Documentation/admin-guide/kernel-parameters.rst). This driver converts
33 capable of DAX (direct-access) file system mappings. See
34 Documentation/driver-api/nvdimm/nvdimm.rst for more details.
69 management sub-system. By default persistent memory does
85 sub-divide a namespace into character devices that can only be
[all …]
|
| /linux-6.12.1/tools/perf/pmu-events/arch/x86/amdzen2/ |
| D | cache.json | 5 …"BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache reads (including har…
11 "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache stores.",
17 "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache shared reads.",
23 "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Instruction cache reads.",
29 …"BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache state change request…
35 "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). PrefetchL2Cmd.",
41 …"BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). L2 Prefetcher. All prefetches a…
64 "BriefDescription": "All L2 Cache Requests (Breakdown 2 - Rare). Data cache read sized.",
70 …"BriefDescription": "All L2 Cache Requests (Breakdown 2 - Rare). Data cache read sized non-cacheab…
76 "BriefDescription": "All L2 Cache Requests (Breakdown 2 - Rare). Instruction cache read sized.",
[all …]
|
| /linux-6.12.1/tools/perf/pmu-events/arch/x86/icelakex/ |
| D | cache.json | 7 …opportunistic replacements, and replacements that require stall-for-replace or block-for-replace.",
45 …non-demand loads and gets hit at least once by demand. The valid outstanding interval is defined u…
78 …"BriefDescription": "Non-modified cache lines that are silently dropped by L2 cache when triggered…
82 …y an L2 cache fill. These lines are typically in Shared or Exclusive state. A non-threaded event.",
100 …from L1D hardware prefetchers). These loads may hit or miss L2 cache. Only non rejected loads are …
163 "PublicDescription": "Counts the RFO (Read-for-Ownership) requests that hit L2 cache.",
172 "PublicDescription": "Counts the RFO (Read-for-Ownership) requests that miss L2 cache.",
204 …"BriefDescription": "Core-originated cacheable requests that missed L3 (Except hardware prefetche…
208 …": "Counts core-originated cacheable requests that miss the L3 cache (Longest Latency cache). Requ…
213 …"BriefDescription": "Core-originated cacheable requests that refer to L3 (Except hardware prefetch…
[all …]
|
| /linux-6.12.1/rust/kernel/alloc/ |
| D | allocator.rs | 1 // SPDX-License-Identifier: GPL-2.0
6 use core::alloc::{GlobalAlloc, Layout};
7 use core::ptr;
15 /// - `ptr` can be either null or a pointer which has been allocated by this allocator.
16 /// - `new_layout` must have a non-zero size.
17 pub(crate) unsafe fn krealloc_aligned(ptr: *mut u8, new_layout: Layout, flags: Flags) -> *mut u8 { in krealloc_aligned()
27 // - `ptr` is either null or a pointer returned from a previous `k{re}alloc()` by the in krealloc_aligned()
29 // - `size` is greater than 0 since it's from `layout.size()` (which cannot be zero according in krealloc_aligned()
31 unsafe { bindings::krealloc(ptr as *const core::ffi::c_void, size, flags.0) as *mut u8 } in krealloc_aligned() constant
35 unsafe fn alloc(&self, layout: Layout) -> *mut u8 { in alloc()
[all …]
|
| /linux-6.12.1/arch/mips/include/asm/ |
| D | pm-cps.h | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */
11 * The CM & CPC can only handle coherence & power control on a per-core basis,
12 * thus in an MT system the VP(E)s within each core are coupled and can only
25 CPS_PM_NC_WAIT, /* MIPS wait instruction, non-coherent */
26 CPS_PM_CLOCK_GATED, /* Core clock gated */
27 CPS_PM_POWER_GATED, /* Core power gated */
32 * cps_pm_support_state - determine whether the system supports a PM state
40 * cps_pm_enter_state - enter a PM state
43 * Enter the given PM state. If coupled_coherence is non-zero then it is
45 * each coupled CPU. Returns 0 on successful entry & exit, otherwise -errno.
|
| /linux-6.12.1/include/uapi/linux/ |
| D | membarrier.h | 31 * enum membarrier_cmd - membarrier system call command
38 * user-space addresses match program order between
40 * (non-running threads are de facto in such a
50 * user-space addresses match program order between
52 * (non-running threads are de facto in such a
60 * non-registered process.
71 * where all memory accesses to user-space
74 * (non-running threads are de facto in such a
79 * the non-expedited ones, they never block,
84 * returns -EPERM.
[all …]
|