mips/kernel/cps-vec.S

1 /* SPDX-License-Identifier: GPL-2.0-or-later */
10 #include <asm/asm-offsets.h>
17 #include <asm/smp-cps.h>
51 	 * Set dest to non-zero if the core supports the MT ASE, else zero. If
66 	 * Set dest to non-zero if the core supports MIPSr6 multithreading
131 	/* Skip core-level init if we started up coherent */
135 	/* Perform any further required core-level initialisation */
140 	 * Boot any other VPEs within this core that should be online, and
195 	/* Check that the core implements the MT ASE */
216 	/* Retrieve the number of VPEs within the core */
226 	/* Loop through each VPE within this core */
236 	/* Set exclusive TC, non-active, master */
242 	/* Set TC non-active, non-allocatable */
267  * mips_cps_get_bootcfg() - retrieve boot configuration pointers
281 	/* Calculate this VPEs ID. If the core doesn't support MT use 0 */
287 	 * Assume non-contiguous numbering. Perhaps some day we'll need
296 	/* Find the number of VPEs present in the core */
308 	addiu	t1, t1, -1
352 	/* If the core doesn't support MT then return */
419 	 * CONFIG3 must exist to be running MT startup - just read it.
506 	/* Detect I-cache line size */
512 	/* Detect I-cache size */
519 1:	/* At this point t1 == I-cache sets per way */
533 	/* Detect D-cache line size */
539 	/* Detect D-cache size */
546 1:	/* At this point t1 == D-cache sets per way */