usb/host/octeon-hcd.h

1 /* SPDX-License-Identifier: GPL-2.0 */
11  * Copyright (c) 2003-2010 Cavium Networks (support@cavium.com). All rights
102  * Core AHB Configuration Register (GAHBCFG)
104  * This register can be used to configure the core after power-on or a change in
105  * mode of operation. This register mainly contains AHB system-related
107  * core. In general, software need not know about this interface except to
110  * The application must program this register as part of the O2P USB core
120 	 *	Core Interrupt register (GINTSTS.PTxFEmp) is triggered. This
126 	 * @nptxfemplvl: Non-Periodic TxFIFO Empty Level (NPTxFEmpLvl)
128 	 *	Indicates when the Non-Periodic TxFIFO Empty Interrupt bit in
129 	 *	the Core Interrupt register (GINTSTS.NPTxFEmp) is triggered.
131 	 *	* 1'b0: GINTSTS.NPTxFEmp interrupt indicates that the Non-
133 	 *	* 1'b1: GINTSTS.NPTxFEmp interrupt indicates that the Non-
136 	 *	* 1'b0: Core operates in Slave mode
137 	 *	* 1'b1: Core operates in a DMA mode
144 	 *	the interrupt status registers are updated by the core.
165  * This register contains the configuration options of the O2P USB core.
172 	 *	This value is in terms of 32-bit words.
182 	 *	* 1'b0: Asynchronous reset is used in the core
183 	 *	* 1'b1: Synchronous reset is used in the core
189 	 *	* 1'b0: Vendor Control Interface is not available on the core.
192 	 *	* 1'b0: I2C Interface is not available on the core.
193 	 *	* 1'b1: I2C Interface is available on the core.
195 	 *	The application uses this bit to indicate the O2P USB core's
211 	 *	- ...
233  * Core Interrupt Mask Register (GINTMSK)
235  * This register works with the Core Interrupt register to interrupt the
237  * that bit will not be generated. However, the Core Interrupt (GINTSTS)
274 	 * @ginnakeffmsk: Global Non-Periodic IN NAK Effective Mask
276 	 * @nptxfempmsk: Non-Periodic TxFIFO Empty Mask (NPTxFEmpMsk)
277 	 * @rxflvlmsk: Receive FIFO Non-Empty Mask (RxFLvlMsk)
322  * Core Interrupt Register (GINTSTS)
324  * This register interrupts the application for system-level events in the
343 	 *	Power-Down and Clock Gating Programming Model" on
351 	 *	Power-Down and Clock Gating Programming Model" on
356 	 *	The core sets this bit when there is a change in connector ID
363 	 *	bit in the Core AHB Configuration register
366 	 *	The core sets this bit to indicate that an interrupt is pending
367 	 *	on one of the channels of the core (in Host mode). The
371 	 *	Channel-n Interrupt (HCINTn) register to determine the exact
375 	 *	The core sets this bit to indicate a change in port status of
376 	 *	one of the O2P USB core ports in Host mode. The application must
383 	 *	indicates that the core has stopped fetching data for IN
388 	 *	In Host mode, the core sets this interrupt bit when there are
392 	 *	The Device mode, the core sets this interrupt to indicate that
398 	 *	The core sets this interrupt to indicate that there is at least
404 	 *	The core sets this bit to indicate that an interrupt is pending
405 	 *	on one of the OUT endpoints of the core (in Device mode). The
409 	 *	corresponding Device OUT Endpoint-n Interrupt (DOEPINTn)
414 	 *	The core sets this bit to indicate that an interrupt is pending
415 	 *	on one of the IN endpoints of the core (in Device mode). The
419 	 *	corresponding Device IN Endpoint-n Interrupt (DIEPINTn)
424 	 *	Indicates that an IN token has been received for a non-periodic
426 	 *	top of the Non-Periodic Transmit FIFO and the IN endpoint
433 	 *	The core sets this bit when it fails to write an isochronous OUT
438 	 *	The core sets this bit to indicate that speed enumeration is
442 	 *	The core sets this bit to indicate that a reset is detected on
445 	 *	The core sets this bit to indicate that a suspend was detected
446 	 *	on the USB. The core enters the Suspended state when there
450 	 *	The core sets this bit to indicate that an Idle state has been
459 	 *	effect in the core. This bit can be cleared by writing the Clear
462 	 * @ginnakeff: Global IN Non-Periodic NAK Effective (GINNakEff)
463 	 *	Indicates that the Set Global Non-Periodic IN NAK bit in the
465 	 *	application, has taken effect in the core. That is, the core has
467 	 *	can be cleared by clearing the Clear Global Non-Periodic IN
472 	 * @nptxfemp: Non-Periodic TxFIFO Empty (NPTxFEmp)
473 	 *	This interrupt is asserted when the Non-Periodic TxFIFO is
475 	 *	one entry to be written to the Non-Periodic Transmit Request
477 	 *	the Non-Periodic TxFIFO Empty Level bit in the Core AHB
479 	 * @rxflvl: RxFIFO Non-Empty (RxFLvl)
483 	 *	In Host mode, the core sets this bit to indicate that an SOF
484 	 *	(FS), micro-SOF (HS), or Keep-Alive (LS) is transmitted on the
487 	 *	In Device mode, in the core sets this bit to indicate that an
490 	 *	number. This interrupt is seen only when the core is operating
493 	 *	The core sets this bit to indicate an OTG protocol event. The
499 	 *	The core sets this bit when the application is trying to access:
500 	 *	* A Host mode register, when the core is operating in Device
502 	 *	* A Device mode register, when the core is operating in Host
505 	 *	response, but is ignored by the core internally and doesn't
506 	 *	affect the operation of the core.
552  * Non-Periodic Transmit FIFO Size Register (GNPTXFSIZ)
555  * Non-Periodic TxFIFO.
561 	 * @nptxfdep: Non-Periodic TxFIFO Depth (NPTxFDep)
562 	 *	This value is in terms of 32-bit words.
565 	 * @nptxfstaddr: Non-Periodic Transmit RAM Start Address (NPTxFStAddr)
566 	 *	This field contains the memory start address for Non-Periodic
579  * Non-Periodic Transmit FIFO/Queue Status Register (GNPTXSTS)
581  * This read-only register contains the free space information for the
582  * Non-Periodic TxFIFO and the Non-Periodic Transmit Request Queue.
588 	 * @nptxqtop: Top of the Non-Periodic Transmit Request Queue (NPTxQTop)
589 	 *	Entry in the Non-Periodic Tx Request Queue that is currently
593 	 *	- 2'b00: IN/OUT token
594 	 *	- 2'b01: Zero-length transmit packet (device IN/host OUT)
595 	 *	- 2'b10: PING/CSPLIT token
596 	 *	- 2'b11: Channel halt command
598 	 * @nptxqspcavail: Non-Periodic Transmit Request Queue Space Available
600 	 *	Indicates the amount of free space available in the Non-
604 	 *	* 8'h0: Non-Periodic Transmit Request Queue is full
609 	 * @nptxfspcavail: Non-Periodic TxFIFO Space Avail (NPTxFSpcAvail)
610 	 *	Indicates the amount of free space available in the Non-
612 	 *	Values are in terms of 32-bit words.
613 	 *	* 16'h0: Non-Periodic TxFIFO is full
632  * Core Reset Register (GRSTCTL)
635  * the core.
648 	 *	Flush bit. This field must not be changed until the core clears
650 	 *	* 5'h0: Non-Periodic TxFIFO flush
654 	 *	- ...
656 	 *	* 5'h10: Flush all the Periodic and Non-Periodic TxFIFOs in the
657 	 *	core
660 	 *	cannot do so if the core is in the midst of a transaction.
662 	 *	core is neither writing to the TxFIFO nor reading from the
664 	 *	The application must wait until the core clears this bit before
669 	 *	must first ensure that the core is not in the middle of a
672 	 *	the core is neither reading from the RxFIFO nor writing to the
682 	 *	counter inside the core. When the (micro)frame counter is reset,
683 	 *	the subsequent SOF sent out by the core will have a
698 	 *	can get the status of any core events that occurred after it set
700 	 *	This is a self-clearing bit that the core clears after all
701 	 *	necessary logic is reset in the core. This may take several
702 	 *	clocks, depending on the core's current state.
703 	 * @csftrst: Core Soft Reset (CSftRst)
707 	 *	- PCGCCTL.RstPdwnModule
708 	 *	- PCGCCTL.GateHclk
709 	 *	- PCGCCTL.PwrClmp
710 	 *	- PCGCCTL.StopPPhyLPwrClkSelclk
711 	 *	- GUSBCFG.PhyLPwrClkSel
712 	 *	- GUSBCFG.DDRSel
713 	 *	- GUSBCFG.PHYSel
714 	 *	- GUSBCFG.FSIntf
715 	 *	- GUSBCFG.ULPI_UTMI_Sel
716 	 *	- GUSBCFG.PHYIf
717 	 *	- HCFG.FSLSPclkSel
718 	 *	- DCFG.DevSpd
727 	 *	the core. This is a self-clearing bit and the core clears this
728 	 *	bit after all the necessary logic is reset in the core, which
730 	 *	core. Once this bit is cleared software should wait at least 3
770 	 *	This value is in terms of 32-bit words.
788  * This Description is only valid when the core is in Host Mode. For Device Mode
791  *	 same offset in the O2P USB core. The offset difference shown in this
830  * Core USB Configuration Register (GUSBCFG)
832  * This register can be used to configure the core after power-on or a changing
833  * to Host mode or Device mode. It contains USB and USB-PHY related
844 	 * @phylpwrclksel: PHY Low-Power Clock Select (PhyLPwrClkSel)
846 	 *	Selects either 480-MHz or 48-MHz (low-power) PHY mode. In
847 	 *	FS and LS modes, the PHY can usually operate on a 48-MHz
849 	 *	* 1'b0: 480-MHz Internal PLL clock
850 	 *	* 1'b1: 48-MHz External Clock
852 	 *	30-MHz, depending upon whether 8- or 16-bit data width is
853 	 *	selected. In 48-MHz mode, the UTMI interface operates at 48
856 	 *	This bit drives the utmi_fsls_low_power core output signal, and
863 	 * @hnpcap: HNP-Capable (HNPCap)
865 	 * @srpcap: SRP-Capable (SRPCap)
869 	 * @physel: USB 2.0 High-Speed PHY or USB 1.1 Full-Speed Serial
871 	 * @fsintf: Full-Speed Serial Interface Select (FSIntf)
879 	 *	field is added to the high-speed/full-speed interpacket timeout
880 	 *	duration in the core to account for any additional delays
884 	 *	The USB standard timeout value for high-speed operation is
886 	 *	value for full-speed operation is 16 to 18 (inclusive) bit
890 	 *	High-speed operation:
891 	 *	* One 30-MHz PHY clock = 16 bit times
892 	 *	* One 60-MHz PHY clock = 8 bit times
893 	 *	Full-speed operation:
894 	 *	* One 30-MHz PHY clock = 0.4 bit times
895 	 *	* One 60-MHz PHY clock = 0.2 bit times
896 	 *	* One 48-MHz PHY clock = 0.25 bit times
923  * the Core Interrupt register (GINTSTS.HChInt). This is shown in Interrupt.
926  * in the corresponding Host Channel-n Interrupt register.
970  * Host Channel-n Characteristics Register (HCCHAR)
998 	 *	When the Split Enable bit of the Host Channel-n Split Control
1018 	 * @lspddev: Low-Speed Device (LSpdDev)
1020 	 *	channel is communicating to a low-speed device.
1052  * This register configures the core after power-on. Do not make changes to this
1059 	 * @fslssupp: FS- and LS-Only Support (FSLSSupp)
1060 	 *	The application uses this bit to control the core's enumeration
1061 	 *	speed. Using this bit, the application can make the core
1067 	 *	* 1'b1: FS/LS-only, even if the connected device can support HS
1069 	 *	When the core is in FS Host mode
1073 	 *	When the core is in LS Host mode
1098  * Host Channel-n Interrupt Register (HCINT)
1100  * This register indicates the status of a channel with respect to USB- and
1101  * AHB-related events. The application must read this register when the Host
1102  * Channels Interrupt bit of the Core Interrupt register (GINTSTS.HChInt) is
1105  * number for the Host Channel-n Interrupt register. The application must clear
1149  * Host Channel-n Interrupt Mask Register (HCINTMSKn)
1191  * Host Channel-n Split Control Register (HCSPLT)
1236  * Host Channel-n Transfer Size Register (HCTSIZ)
1252 	 *	* 2'b11: MDATA (non-control)/SETUP (control)
1266 	 *	size for IN transactions (periodic and non-periodic).
1283  * which the O2P USB core has enumerated.
1291 	 *	the interval between two consecutive SOFs (FS) or micro-
1292 	 *	SOFs (HS) or Keep-Alive tokens (HS). This field contains the
1298 	 *	has been set. If no value is programmed, the core calculates
1350  * A single register holds USB port-related information such as USB reset,
1353  * through the Host Port Interrupt bit of the Core Interrupt register
1379 	 *	PrtSpd must be zero (i.e. the interface must be in high-speed
1383 	 *	and the core clears this bit on an overcurrent condition.
1388 	 *	* Bit [10]: Logic level of D-
1407 	 *	mode. The core only stops sending SOFs when this is set.
1412 	 *	status of the port. This bit is cleared by the core after a
1416 	 *	Disconnect Detected Interrupt bit in the Core Interrupt
1423 	 *	the port. The core continues to drive the resume signal
1425 	 *	If the core detects a USB remote wakeup sequence, as
1427 	 *	Interrupt bit of the Core Interrupt register
1428 	 *	(GINTSTS.WkUpInt), the core starts driving resume
1431 	 *	this bit indicates whether the core is currently driving
1436 	 *	The core sets this bit when the status of the Port
1443 	 *	The core sets this bit when the status of the Port Enable bit
1446 	 *	A port is enabled only by the core after a reset sequence,
1455 	 *	The core sets this bit when a device connection is detected
1457 	 *	Interrupt bit of the Core Interrupt register (GINTSTS.PrtInt).
1497 	 *	This value is in terms of 32-bit words.
1514  * This read-only register contains the free space information for the Periodic
1526 	 *	- 1'b0: send in even (micro)frame
1527 	 *	- 1'b1: send in odd (micro)frame
1530 	 *	- 2'b00: IN/OUT
1531 	 *	- 2'b01: Zero-length packet
1532 	 *	- 2'b10: CSPLIT
1533 	 *	- 2'b11: Disable channel command
1550 	 *	Values are in terms of 32-bit words
1585 	 * @hclk_rst: When this field is '0' the HCLK-DIVIDER used to
1590 	 *	when core reset is asserted.
1591 	 * @p_x_on: Force USB-PHY on during suspend.
1592 	 *	'1' USB-PHY XO block is powered-down during
1594 	 *	'0' USB-PHY XO block is powered-up during
1600 	 *		'0' The USB-PHY uses a 12MHz crystal as a clock source
1615 	 * @p_com_on: '0' Force USB-PHY XO Bias, Bandgap and PLL to
1617 	 *	'1' The USB-PHY XO Bias, Bandgap and PLL are
1698 	 * @txhsxvtune: Transmitter High-Speed Crossover Adjustment
1705 	 * @lsbist: Low-Speed BIST Enable.
1706 	 * @fsbist: Full-Speed BIST Enable.
1707 	 * @hsbist: High-Speed BIST Enable.
1717 	 * @siddq: Drives the USBP (USB-PHY) SIDDQ input.
1721 	 *	- still provide 3.3V to USB_VDD33, and
1722 	 *	- tie USB_REXT to 3.3V supply, and
1723 	 *	- set USBN*_USBP_CTL_STATUS[SIDDQ]=1
1724 	 * @txpreemphasistune: HS Transmitter Pre-Emphasis Enable
1726 	 *	with byte-counts between packets. When set to 0
1728 	 *	4-byte aligned address after adding byte-count.
1729 	 * @usbc_end: Bigendian input to the USB Core. This should be
1733 	 * @dp_pulld: PHY DP_PULLDOWN input to the USB-PHY.
1734 	 *	This signal enables the pull-down resistance on
1735 	 *	the D+ line. '1' pull down-resistance is connected
1738 	 *	(downstream-facing port), dp_pulldown and
1741 	 * @dm_pulld: PHY DM_PULLDOWN input to the USB-PHY.
1742 	 *	This signal enables the pull-down resistance on
1743 	 *	the D- line. '1' pull down-resistance is connected
1744 	 *	to D-. '0' pull down resistance is not connected
1745 	 *	to D-. When an A/B device is acting as a host
1746 	 *	(downstream-facing port), dp_pulldown and
1752 	 * @tuning: Transmitter Tuning for High-Speed Operation.
1754 	 *	times for high-speed operation.
1769 	 *	when bit-stuffing is enabled.
1772 	 *	when bit-stuffing is enabled.
1783 	 * @bist_enb: Built-In Self Test Enable.
1797 	 *	This is a test signal. When the USB Core is
1800 	 *	free_clk, then re-enable them with an aligned
1805 	 *	de-assertion.