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/linux-6.12.1/Documentation/devicetree/bindings/media/i2c/
Dst,st-mipid02.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/media/i2c/st,st-mipid02.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: STMicroelectronics MIPID02 CSI-2 to PARALLEL bridge
10 - Benjamin Mugnier <benjamin.mugnier@foss.st.com>
11 - Sylvain Petinot <sylvain.petinot@foss.st.com>
14 MIPID02 has two CSI-2 input ports, only one of those ports can be
15 active at a time. Active port input stream will be de-serialized
17 CSI-2 first input port is a dual lane 800Mbps per lane whereas CSI-2
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/linux-6.12.1/Documentation/devicetree/bindings/display/bridge/
Dtoshiba,tc358775.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Vinay Simha BN <simhavcs@gmail.com>
15 MIPI DSI-RX Data 4-lane, CLK 1-lane with data rates up to 800 Mbps/lane.
17 Up to 1600x1200 24-bit/pixel resolution for single-link LVDS display panel
19 Up to WUXGA (1920x1200 24-bit pixels) resolution for dual-link LVDS display
25 - toshiba,tc358765
26 - toshiba,tc358775
32 vdd-supply:
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Dti,sn65dsi83.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Marek Vasut <marex@denx.de>
13 Texas Instruments SN65DSI83 1x Single-link MIPI DSI
14 to 1x Single-link LVDS
16 Texas Instruments SN65DSI84 1x Single-link MIPI DSI
17 to 1x Dual-link or 2x Single-link LVDS
23 - ti,sn65dsi83
24 - ti,sn65dsi84
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/linux-6.12.1/drivers/net/dsa/b53/
Db53_serdes.c1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
42 static void b53_serdes_set_lane(struct b53_device *dev, u8 lane) in b53_serdes_set_lane() argument
44 if (dev->serdes_lane == lane) in b53_serdes_set_lane()
47 WARN_ON(lane > 1); in b53_serdes_set_lane()
50 SERDES_XGXSBLK0_BLOCKADDRESS, lane); in b53_serdes_set_lane()
51 dev->serdes_lane = lane; in b53_serdes_set_lane()
54 static void b53_serdes_write(struct b53_device *dev, u8 lane, in b53_serdes_write() argument
57 b53_serdes_set_lane(dev, lane); in b53_serdes_write()
61 static u16 b53_serdes_read(struct b53_device *dev, u8 lane, in b53_serdes_read() argument
64 b53_serdes_set_lane(dev, lane); in b53_serdes_read()
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/linux-6.12.1/include/linux/phy/
Dphy-lvds.h1 /* SPDX-License-Identifier: GPL-2.0 */
10 * struct phy_configure_opts_lvds - LVDS configuration set
11 * @bits_per_lane_and_dclk_cycle: Number of bits per lane per differential
16 * data lanes, starting from lane 0,
20 * phy to support dual link transmission,
/linux-6.12.1/drivers/phy/intel/
Dphy-intel-lgm-combo.c1 // SPDX-License-Identifier: GPL-2.0
3 * Intel Combo-PHY driver
5 * Copyright (C) 2019-2020 Intel Corporation.
20 #include <dt-bindings/phy/phy.h>
33 #define CR_ADDR(addr, lane) (((addr) + (lane) * 0x100) << 2) argument
37 #define COMBO_PHY_ID(x) ((x)->parent->id)
38 #define PHY_ID(x) ((x)->id)
107 struct intel_combo_phy *cbphy = iphy->parent; in intel_cbphy_iphy_enable()
108 u32 mask = BIT(cbphy->phy_mode * 2 + iphy->id); in intel_cbphy_iphy_enable()
114 return regmap_update_bits(cbphy->hsiocfg, REG_CLK_DISABLE(cbphy->bid), in intel_cbphy_iphy_enable()
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/linux-6.12.1/drivers/gpu/drm/bridge/
Dtc358775.c1 // SPDX-License-Identifier: GPL-2.0
16 #include <linux/media-bus-format.h>
36 /* DSI D-PHY Layer Registers */
37 #define D0W_DPHYCONTTX 0x0004 /* Data Lane 0 DPHY Tx Control */
38 #define CLW_DPHYCONTRX 0x0020 /* Clock Lane DPHY Rx Control */
39 #define D0W_DPHYCONTRX 0x0024 /* Data Lane 0 DPHY Rx Control */
40 #define D1W_DPHYCONTRX 0x0028 /* Data Lane 1 DPHY Rx Control */
41 #define D2W_DPHYCONTRX 0x002C /* Data Lane 2 DPHY Rx Control */
42 #define D3W_DPHYCONTRX 0x0030 /* Data Lane 3 DPHY Rx Control */
44 #define CLW_CNTRL 0x0040 /* Clock Lane Control */
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Dtc358762.c1 // SPDX-License-Identifier: GPL-2.0
35 #define PPI_D0S_CLRSIPOCOUNT 0x0164 /* Assertion timer for Lane 0 */
36 #define PPI_D1S_CLRSIPOCOUNT 0x0168 /* Assertion timer for Lane 1 */
40 #define DSI_STARTDSI 0x0204 /* START control bit of DSI-TX */
41 #define DSI_LANEENABLE 0x0210 /* Enables each lane */
66 /* Lane enable PPI and DSI register bits */
84 int ret = ctx->error; in tc358762_clear_error()
86 ctx->error = 0; in tc358762_clear_error()
92 struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev); in tc358762_write()
96 if (ctx->error) in tc358762_write()
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/linux-6.12.1/Documentation/devicetree/bindings/connector/
Dusb-connector.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/connector/usb-connector.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Rob Herring <robh@kernel.org>
20 - enum:
21 - usb-a-connector
22 - usb-b-connector
23 - usb-c-connector
25 - items:
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/linux-6.12.1/drivers/gpu/drm/
Ddrm_of.c1 // SPDX-License-Identifier: GPL-2.0-only
5 #include <linux/media-bus-format.h>
25 * drm_of_crtc_port_mask - find the mask of a registered CRTC by port OF node
39 if (tmp->port == port) in drm_of_crtc_port_mask()
50 * drm_of_find_possible_crtcs - find the possible CRTCs for an encoder port
83 * drm_of_component_match_add - Add a component helper OF node match rule
101 * drm_of_component_probe - Generic probe function for a component based master
121 if (!dev->of_node) in drm_of_component_probe()
122 return -EINVAL; in drm_of_component_probe()
129 port = of_parse_phandle(dev->of_node, "ports", i); in drm_of_component_probe()
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/linux-6.12.1/drivers/gpu/drm/i915/display/
Dicl_dsi.c72 drm_err(&dev_priv->drm, "DSI header credits not released\n"); in wait_for_header_credits()
84 drm_err(&dev_priv->drm, "DSI payload credits not released\n"); in wait_for_payload_credits()
101 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in wait_for_cmds_dispatched_to_panel()
109 for_each_dsi_port(port, intel_dsi->ports) { in wait_for_cmds_dispatched_to_panel()
116 for_each_dsi_port(port, intel_dsi->ports) { in wait_for_cmds_dispatched_to_panel()
117 dsi = intel_dsi->dsi_hosts[port]->device; in wait_for_cmds_dispatched_to_panel()
118 dsi->mode_flags |= MIPI_DSI_MODE_LPM; in wait_for_cmds_dispatched_to_panel()
119 dsi->channel = 0; in wait_for_cmds_dispatched_to_panel()
122 drm_err(&dev_priv->drm, in wait_for_cmds_dispatched_to_panel()
127 for_each_dsi_port(port, intel_dsi->ports) { in wait_for_cmds_dispatched_to_panel()
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Dintel_dpio_phy.c2 * Copyright © 2014-2016 Intel Corporation
45 * IOSF-SB port.
48 * houses a common lane part which contains the PLL and other common
49 * logic. CH0 common lane also contains the IOSF-SB logic for the
59 * each spline is made up of one Physical Access Coding Sub-Layer
64 * Additionally the PHY also contains an AUX lane with AUX blocks
70 * Generally on VLV/CHV the common lane corresponds to the pipe and
73 * For dual channel PHY (VLV/CHV):
102 * Dual channel PHY (VLV/CHV/BXT)
103 * ---------------------------------
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/linux-6.12.1/drivers/ufs/host/
Dtc-dwc-g210.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2015-2016 Synopsys, Inc. (www.synopsys.com)
15 #include "ufshcd-dwc.h"
16 #include "ufshci-dwc.h"
17 #include "tc-dwc-g210.h"
20 * tc_dwc_g210_setup_40bit_rmmi() - configure 40-bit RMMI.
23 * Return: 0 on success or non-zero value on failure.
83 * tc_dwc_g210_setup_20bit_rmmi_lane0() - configure 20-bit RMMI Lane 0.
86 * Return: 0 on success or non-zero value on failure.
135 * tc_dwc_g210_setup_20bit_rmmi_lane1() - configure 20-bit RMMI Lane 1.
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/linux-6.12.1/include/linux/
Dthunderbolt.h1 /* SPDX-License-Identifier: GPL-2.0 */
39 * enum tb_security_level - Thunderbolt security level
60 * struct tb - main thunderbolt bus structure
96 return (link - 1) / TB_LINKS_PER_PHY_PORT; in tb_phy_port_from_link()
100 * struct tb_property_dir - XDomain property directory
122 * struct tb_property - XDomain property
174 * enum tb_link_width - Thunderbolt/USB4 link width
175 * @TB_LINK_WIDTH_SINGLE: Single lane link
176 * @TB_LINK_WIDTH_DUAL: Dual lane symmetric link
177 * @TB_LINK_WIDTH_ASYM_TX: Dual lane asymmetric Gen 4 link with 3 transmitters
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/linux-6.12.1/drivers/thunderbolt/
Dclx.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2020 - 2023, Intel Corporation
16 MODULE_PARM_DESC(clx, "allow low power states on the high-speed lanes (default: true)");
44 port->cap_phy + LANE_ADP_CS_1, 1); in tb_port_pm_secondary_set()
54 port->cap_phy + LANE_ADP_CS_1, 1); in tb_port_pm_secondary_set()
73 /* Don't enable CLx in case of two single-lane links */ in tb_port_clx_supported()
74 if (!port->bonded && port->dual_link_port) in tb_port_clx_supported()
77 /* Don't enable CLx in case of inter-domain link */ in tb_port_clx_supported()
78 if (port->xdomain) in tb_port_clx_supported()
81 if (tb_switch_is_usb4(port->sw)) { in tb_port_clx_supported()
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Dswitch.c1 // SPDX-License-Identifier: GPL-2.0
3 * Thunderbolt driver - switch/port utility functions
12 #include <linux/nvmem-provider.h>
42 if (uuid_equal(&st->uuid, sw->uuid)) in __nvm_get_auth_status()
57 *status = st ? st->status : 0; in nvm_get_auth_status()
64 if (WARN_ON(!sw->uuid)) in nvm_set_auth_status()
75 memcpy(&st->uuid, sw->uuid, sizeof(st->uuid)); in nvm_set_auth_status()
76 INIT_LIST_HEAD(&st->list); in nvm_set_auth_status()
77 list_add_tail(&st->list, &nvm_auth_status_cache); in nvm_set_auth_status()
80 st->status = status; in nvm_set_auth_status()
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/linux-6.12.1/Documentation/devicetree/bindings/phy/
Dintel,combo-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/intel,combo-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Dilip Kota <eswara.kota@linux.intel.com>
18 pattern: "combophy(@.*|-([0-9]|[1-9][0-9]+))?$"
22 - const: intel,combophy-lgm
23 - const: intel,combo-phy
30 - description: ComboPhy core registers
31 - description: PCIe app core control registers
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/linux-6.12.1/drivers/gpu/drm/amd/display/include/
Dgrph_object_ctrl_defs.h2 * Copyright 2012-15 Advanced Micro Devices, Inc.
179 uint32_t dp_phy_ref_clk; /* in KHz - DCE12 only */
180 uint32_t i2c_engine_ref_clk; /* in KHz - DCE12 only */
242 uint8_t lane0:2; /* Mapping for lane 0 */
243 uint8_t lane1:2; /* Mapping for lane 1 */
244 uint8_t lane2:2; /* Mapping for lane 2 */
245 uint8_t lane3:2; /* Mapping for lane 3 */
263 /* Secondary transmitter configuration for Dual-link DVI */
425 * DFS-bypass flag
433 INVALID_BACKLIGHT = -1
/linux-6.12.1/Documentation/devicetree/bindings/display/mediatek/
Dmediatek,dsi.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Chun-Kuang Hu <chunkuang.hu@kernel.org>
11 - Philipp Zabel <p.zabel@pengutronix.de>
12 - Jitao Shi <jitao.shi@mediatek.com>
16 drive up to 4-lane MIPI DSI output. Two DSIs can be synchronized for dual-
20 - $ref: /schemas/display/dsi-controller.yaml#
25 - enum:
26 - mediatek,mt2701-dsi
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/linux-6.12.1/drivers/net/pcs/
Dpcs-lynx.c1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
8 #include <linux/pcs-lynx.h>
36 #define lynx_to_phylink_pcs(lynx) (&(lynx)->pcs)
41 struct mii_bus *bus = pcs->bus; in lynx_pcs_get_state_usxgmii()
42 int addr = pcs->addr; in lynx_pcs_get_state_usxgmii()
49 state->link = !!(status & MDIO_STAT1_LSTATUS); in lynx_pcs_get_state_usxgmii()
50 state->an_complete = !!(status & MDIO_AN_STAT1_COMPLETE); in lynx_pcs_get_state_usxgmii()
51 if (!state->link || !state->an_complete) in lynx_pcs_get_state_usxgmii()
68 state->link = false; in lynx_pcs_get_state_2500basex()
72 state->link = !!(bmsr & BMSR_LSTATUS); in lynx_pcs_get_state_2500basex()
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/linux-6.12.1/drivers/gpu/drm/bridge/synopsys/
Ddw-mipi-dsi.c1 // SPDX-License-Identifier: GPL-2.0+
8 * Rockchip version from rockchip/dw-mipi-dsi.c with phy & bridge APIs.
16 #include <linux/media-bus-format.h>
196 #define N_LANES(n) (((n) - 1) & 0x3)
252 unsigned int lane_mbps; /* per lane */
268 struct dw_mipi_dsi *master; /* dual-dsi master ptr */
269 struct dw_mipi_dsi *slave; /* dual-dsi slave ptr */
280 return dsi->slave || dsi->master; in dw_mipi_is_dual_mode()
308 writel(val, dsi->base + reg); in dsi_write()
313 return readl(dsi->base + reg); in dsi_read()
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/linux-6.12.1/drivers/phy/rockchip/
Dphy-rockchip-dphy-rx0.c1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
11 * chromeos-4.4 branch.
14 * Jacob Chen <jacob2.chen@rock-chips.com>
15 * Shunqian Zheng <zhengsq@rock-chips.com>
25 #include <linux/phy/phy-mipi-dphy.h>
64 "dphy-ref",
65 "dphy-cfg",
110 { .offset = _offset, .mask = BIT(_width) - 1, .shift = _shift, }
162 const struct dphy_reg *reg = &priv->drv_data->regs[index]; in rk_dphy_write_grf()
164 unsigned int val = (value << reg->shift) | in rk_dphy_write_grf()
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/linux-6.12.1/drivers/phy/cadence/
Dphy-cadence-torrent.c1 // SPDX-License-Identifier: GPL-2.0-only
9 #include <dt-bindings/phy/phy.h>
10 #include <dt-bindings/phy/phy-cadence.h>
12 #include <linux/clk-provider.h>
168 /* PMA TX Lane registers */
189 /* PMA RX Lane registers */
228 /* PHY PCS lane registers */
239 [CDNS_TORRENT_REFCLK_DRIVER] = "refclk-driver",
240 [CDNS_TORRENT_DERIVED_REFCLK] = "refclk-der",
241 [CDNS_TORRENT_RECEIVED_REFCLK] = "refclk-rec",
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/linux-6.12.1/Documentation/ABI/testing/
Dsysfs-bus-usb10 This allows to avoid side-effects with drivers
28 drivers, non-authorized one are not. By default, wired
33 Contact: linux-usb@vger.kernel.org
67 What: /sys/bus/usb-serial/drivers/.../new_id
69 Contact: linux-usb@vger.kernel.org
72 extra bus folder "usb-serial" in sysfs; apart from that
97 If CONFIG_PM is set and a USB 2.0 lpm-capable device is plugged
113 If CONFIG_PM is set and a USB 3.0 lpm-capable device is plugged
141 attribute allows user-space to know whether the device is
145 an on-screen keyboard if the only wireless keyboard is
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/linux-6.12.1/drivers/gpu/drm/stm/
Dlvds.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2023, STMicroelectronics - All Rights Reserved
4 * Author(s): Raphaël GALLAIS-POU <raphael.gallais-pou@foss.st.com> for STMicroelectronics.
16 #include <linux/clk-provider.h>
19 #include <linux/media-bus-format.h>
62 #define CR_LK1POL GENMASK(20, 16) /* Link-1 output Polarity */
63 #define CR_LK2POL GENMASK(25, 21) /* Link-2 output Polarity */
73 #define CDLCR_DISTR0 GENMASK(3, 0) /* Channel distribution for lane 0 */
74 #define CDLCR_DISTR1 GENMASK(7, 4) /* Channel distribution for lane 1 */
75 #define CDLCR_DISTR2 GENMASK(11, 8) /* Channel distribution for lane 2 */
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