1 // SPDX-License-Identifier: GPL-2.0+
8  * Rockchip version from rockchip/dw-mipi-dsi.c with phy & bridge APIs.
16 #include <linux/media-bus-format.h>
196 #define N_LANES(n)			(((n) - 1) & 0x3)
252 	unsigned int lane_mbps; /* per lane */
268 	struct dw_mipi_dsi *master; /* dual-dsi master ptr */
269 	struct dw_mipi_dsi *slave; /* dual-dsi slave ptr */
280 	return dsi->slave || dsi->master;  in dw_mipi_is_dual_mode()
308 	writel(val, dsi->base + reg);  in dsi_write()
313 	return readl(dsi->base + reg);  in dsi_read()
320 	const struct dw_mipi_dsi_plat_data *pdata = dsi->plat_data;  in dw_mipi_dsi_host_attach()
324 	if (device->lanes > dsi->plat_data->max_data_lanes) {  in dw_mipi_dsi_host_attach()
325 		dev_err(dsi->dev, "the number of data lanes(%u) is too many\n",  in dw_mipi_dsi_host_attach()
326 			device->lanes);  in dw_mipi_dsi_host_attach()
327 		return -EINVAL;  in dw_mipi_dsi_host_attach()
330 	dsi->lanes = device->lanes;  in dw_mipi_dsi_host_attach()
331 	dsi->channel = device->channel;  in dw_mipi_dsi_host_attach()
332 	dsi->format = device->format;  in dw_mipi_dsi_host_attach()
333 	dsi->mode_flags = device->mode_flags;  in dw_mipi_dsi_host_attach()
335 	bridge = devm_drm_of_get_bridge(dsi->dev, dsi->dev->of_node, 1, 0);  in dw_mipi_dsi_host_attach()
339 	bridge->pre_enable_prev_first = true;  in dw_mipi_dsi_host_attach()
340 	dsi->panel_bridge = bridge;  in dw_mipi_dsi_host_attach()
342 	drm_bridge_add(&dsi->bridge);  in dw_mipi_dsi_host_attach()
344 	if (pdata->host_ops && pdata->host_ops->attach) {  in dw_mipi_dsi_host_attach()
345 		ret = pdata->host_ops->attach(pdata->priv_data, device);  in dw_mipi_dsi_host_attach()
357 	const struct dw_mipi_dsi_plat_data *pdata = dsi->plat_data;  in dw_mipi_dsi_host_detach()
360 	if (pdata->host_ops && pdata->host_ops->detach) {  in dw_mipi_dsi_host_detach()
361 		ret = pdata->host_ops->detach(pdata->priv_data, device);  in dw_mipi_dsi_host_detach()
366 	drm_of_panel_bridge_remove(host->dev->of_node, 1, 0);  in dw_mipi_dsi_host_detach()
368 	drm_bridge_remove(&dsi->bridge);  in dw_mipi_dsi_host_detach()
376 	bool lpm = msg->flags & MIPI_DSI_MSG_USE_LPM;  in dw_mipi_message_config()
382 	 * should be computed according to byte lane, lane number and only  in dw_mipi_message_config()
388 	if (msg->flags & MIPI_DSI_MSG_REQ_ACK)  in dw_mipi_message_config()
408 	ret = readl_poll_timeout(dsi->base + DSI_CMD_PKT_STATUS,  in dw_mipi_dsi_gen_pkt_hdr_write()
412 		dev_err(dsi->dev, "failed to get available command FIFO\n");  in dw_mipi_dsi_gen_pkt_hdr_write()
419 	ret = readl_poll_timeout(dsi->base + DSI_CMD_PKT_STATUS,  in dw_mipi_dsi_gen_pkt_hdr_write()
423 		dev_err(dsi->dev, "failed to write command FIFO\n");  in dw_mipi_dsi_gen_pkt_hdr_write()
433 	const u8 *tx_buf = packet->payload;  in dw_mipi_dsi_write()
434 	int len = packet->payload_length, pld_data_bytes = sizeof(u32), ret;  in dw_mipi_dsi_write()
448 			len -= pld_data_bytes;  in dw_mipi_dsi_write()
451 		ret = readl_poll_timeout(dsi->base + DSI_CMD_PKT_STATUS,  in dw_mipi_dsi_write()
455 			dev_err(dsi->dev,  in dw_mipi_dsi_write()
462 	memcpy(&word, packet->header, sizeof(packet->header));  in dw_mipi_dsi_write()
469 	int i, j, ret, len = msg->rx_len;  in dw_mipi_dsi_read()
470 	u8 *buf = msg->rx_buf;  in dw_mipi_dsi_read()
474 	ret = readl_poll_timeout(dsi->base + DSI_CMD_PKT_STATUS,  in dw_mipi_dsi_read()
478 		dev_err(dsi->dev, "Timeout during read operation\n");  in dw_mipi_dsi_read()
484 		ret = readl_poll_timeout(dsi->base + DSI_CMD_PKT_STATUS,  in dw_mipi_dsi_read()
488 			dev_err(dsi->dev, "Read payload FIFO is empty\n");  in dw_mipi_dsi_read()
509 		dev_err(dsi->dev, "failed to create packet: %d\n", ret);  in dw_mipi_dsi_host_transfer()
514 	if (dsi->slave)  in dw_mipi_dsi_host_transfer()
515 		dw_mipi_message_config(dsi->slave, msg);  in dw_mipi_dsi_host_transfer()
520 	if (dsi->slave) {  in dw_mipi_dsi_host_transfer()
521 		ret = dw_mipi_dsi_write(dsi->slave, &packet);  in dw_mipi_dsi_host_transfer()
526 	if (msg->rx_buf && msg->rx_len) {  in dw_mipi_dsi_host_transfer()
530 		nb_bytes = msg->rx_len;  in dw_mipi_dsi_host_transfer()
553 	const struct dw_mipi_dsi_plat_data *pdata = dsi->plat_data;  in dw_mipi_dsi_bridge_atomic_get_input_bus_fmts()
556 	if (pdata->get_input_bus_fmts)  in dw_mipi_dsi_bridge_atomic_get_input_bus_fmts()
557 		return pdata->get_input_bus_fmts(pdata->priv_data,  in dw_mipi_dsi_bridge_atomic_get_input_bus_fmts()
578 	const struct dw_mipi_dsi_plat_data *pdata = dsi->plat_data;  in dw_mipi_dsi_bridge_atomic_check()
581 	bridge_state->input_bus_cfg.flags =  in dw_mipi_dsi_bridge_atomic_check()
584 	if (pdata->mode_fixup) {  in dw_mipi_dsi_bridge_atomic_check()
585 		ret = pdata->mode_fixup(pdata->priv_data, &crtc_state->mode,  in dw_mipi_dsi_bridge_atomic_check()
586 					&crtc_state->adjusted_mode);  in dw_mipi_dsi_bridge_atomic_check()
589 					 DRM_MODE_ARG(&crtc_state->mode));  in dw_mipi_dsi_bridge_atomic_check()
590 			return -EINVAL;  in dw_mipi_dsi_bridge_atomic_check()
603 	 * enabling low power is panel-dependent, we should use the  in dw_mipi_dsi_video_mode_config()
608 	if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_BURST)  in dw_mipi_dsi_video_mode_config()
610 	else if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE)  in dw_mipi_dsi_video_mode_config()
616 	if (dsi->vpg_defs.vpg) {  in dw_mipi_dsi_video_mode_config()
618 		val |= dsi->vpg_defs.vpg_horizontal ?  in dw_mipi_dsi_video_mode_config()
620 		val |= dsi->vpg_defs.vpg_ber_pattern ? VID_MODE_VPG_MODE : 0;  in dw_mipi_dsi_video_mode_config()
642 	if (dsi->mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS)  in dw_mipi_dsi_set_mode()
657 	const struct dw_mipi_dsi_phy_ops *phy_ops = dsi->plat_data->phy_ops;  in dw_mipi_dsi_init()
666 	if (phy_ops->get_esc_clk_rate) {  in dw_mipi_dsi_init()
667 		ret = phy_ops->get_esc_clk_rate(dsi->plat_data->priv_data,  in dw_mipi_dsi_init()
680 	esc_clk_division = (dsi->lane_mbps >> 3) / esc_rate + 1;  in dw_mipi_dsi_init()
687 	 * high speed transmission counter timeout and byte lane...  in dw_mipi_dsi_init()
698 	switch (dsi->format) {  in dw_mipi_dsi_dpi_config()
713 	if (mode->flags & DRM_MODE_FLAG_NVSYNC)  in dw_mipi_dsi_dpi_config()
715 	if (mode->flags & DRM_MODE_FLAG_NHSYNC)  in dw_mipi_dsi_dpi_config()
718 	dsi_write(dsi, DSI_DPI_VCID, DPI_VCID(dsi->channel));  in dw_mipi_dsi_dpi_config()
727 	if (dsi->mode_flags & MIPI_DSI_MODE_NO_EOT_PACKET)  in dw_mipi_dsi_packet_handler_config()
738 	 * only burst mode is supported here. For non-burst video modes,  in dw_mipi_dsi_video_packet_config()
741 	 * non-burst video modes, see dw_mipi_dsi_video_mode_config()...  in dw_mipi_dsi_video_packet_config()
746 				VID_PKT_SIZE(mode->hdisplay / 2) :  in dw_mipi_dsi_video_packet_config()
747 				VID_PKT_SIZE(mode->hdisplay));  in dw_mipi_dsi_video_packet_config()
755 	 * to the timeout clock division (TO_CLK_DIVISION) and byte lane...  in dw_mipi_dsi_command_mode_config()
760 	 * the Bus-Turn-Around Timeout Counter should be computed  in dw_mipi_dsi_command_mode_config()
761 	 * according to byte lane...  in dw_mipi_dsi_command_mode_config()
771 	return minimum_lbccs[dsi->lanes - 1];  in dw_mipi_dsi_get_minimum_lbcc()
774 /* Get lane byte clock cycles. */
782 	if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_BURST) {  in dw_mipi_dsi_get_hcomponent_lbcc()
784 		lbcc = hcomponent * dsi->lane_mbps * MSEC_PER_SEC / 8;  in dw_mipi_dsi_get_hcomponent_lbcc()
787 		bpp = mipi_dsi_pixel_format_to_bpp(dsi->format);  in dw_mipi_dsi_get_hcomponent_lbcc()
789 			dev_err(dsi->dev, "failed to get bpp\n");  in dw_mipi_dsi_get_hcomponent_lbcc()
793 		lbcc = div_u64((u64)hcomponent * mode->clock * bpp, dsi->lanes * 8);  in dw_mipi_dsi_get_hcomponent_lbcc()
796 	frac = lbcc % mode->clock;  in dw_mipi_dsi_get_hcomponent_lbcc()
797 	lbcc = lbcc / mode->clock;  in dw_mipi_dsi_get_hcomponent_lbcc()
814 	htotal = mode->htotal;  in dw_mipi_dsi_line_timer_config()
815 	hsa = mode->hsync_end - mode->hsync_start;  in dw_mipi_dsi_line_timer_config()
816 	hbp = mode->htotal - mode->hsync_end;  in dw_mipi_dsi_line_timer_config()
837 	vactive = mode->vdisplay;  in dw_mipi_dsi_vertical_timing_config()
838 	vsa = mode->vsync_end - mode->vsync_start;  in dw_mipi_dsi_vertical_timing_config()
839 	vfp = mode->vsync_start - mode->vdisplay;  in dw_mipi_dsi_vertical_timing_config()
840 	vbp = mode->vtotal - mode->vsync_end;  in dw_mipi_dsi_vertical_timing_config()
850 	const struct dw_mipi_dsi_phy_ops *phy_ops = dsi->plat_data->phy_ops;  in dw_mipi_dsi_dphy_timing_config()
855 	ret = phy_ops->get_timing(dsi->plat_data->priv_data,  in dw_mipi_dsi_dphy_timing_config()
856 				  dsi->lane_mbps, &timing);  in dw_mipi_dsi_dphy_timing_config()
858 		DRM_DEV_ERROR(dsi->dev, "Retrieving phy timings failed\n");  in dw_mipi_dsi_dphy_timing_config()
862 	 * data & clock lane timers should be computed according to panel  in dw_mipi_dsi_dphy_timing_config()
863 	 * blankings and to the automatic clock lane control mode...  in dw_mipi_dsi_dphy_timing_config()
895 		  N_LANES(dsi->lanes));  in dw_mipi_dsi_dphy_interface_config()
916 	ret = readl_poll_timeout(dsi->base + DSI_PHY_STATUS, val,  in dw_mipi_dsi_dphy_enable()
921 	ret = readl_poll_timeout(dsi->base + DSI_PHY_STATUS,  in dw_mipi_dsi_dphy_enable()
925 		DRM_DEBUG_DRIVER("failed to wait phy clk lane stop state\n");  in dw_mipi_dsi_dphy_enable()
940 	const struct dw_mipi_dsi_phy_ops *phy_ops = dsi->plat_data->phy_ops;  in dw_mipi_dsi_bridge_post_atomic_disable()
943 	 * Switch to command mode before panel-bridge post_disable &  in dw_mipi_dsi_bridge_post_atomic_disable()
945 	 * Note: panel-bridge disable & panel disable has been called  in dw_mipi_dsi_bridge_post_atomic_disable()
950 	if (phy_ops->power_off)  in dw_mipi_dsi_bridge_post_atomic_disable()
951 		phy_ops->power_off(dsi->plat_data->priv_data);  in dw_mipi_dsi_bridge_post_atomic_disable()
953 	if (dsi->slave) {  in dw_mipi_dsi_bridge_post_atomic_disable()
954 		dw_mipi_dsi_disable(dsi->slave);  in dw_mipi_dsi_bridge_post_atomic_disable()
955 		clk_disable_unprepare(dsi->slave->pclk);  in dw_mipi_dsi_bridge_post_atomic_disable()
956 		pm_runtime_put(dsi->slave->dev);  in dw_mipi_dsi_bridge_post_atomic_disable()
960 	clk_disable_unprepare(dsi->pclk);  in dw_mipi_dsi_bridge_post_atomic_disable()
961 	pm_runtime_put(dsi->dev);  in dw_mipi_dsi_bridge_post_atomic_disable()
967 	if (dsi->master)  in dw_mipi_dsi_get_lanes()
968 		return dsi->master->lanes + dsi->lanes;  in dw_mipi_dsi_get_lanes()
971 	if (dsi->slave)  in dw_mipi_dsi_get_lanes()
972 		return dsi->lanes + dsi->slave->lanes;  in dw_mipi_dsi_get_lanes()
974 	/* single-dsi, so no other instance to consider */  in dw_mipi_dsi_get_lanes()
975 	return dsi->lanes;  in dw_mipi_dsi_get_lanes()
981 	const struct dw_mipi_dsi_phy_ops *phy_ops = dsi->plat_data->phy_ops;  in dw_mipi_dsi_mode_set()
982 	void *priv_data = dsi->plat_data->priv_data;  in dw_mipi_dsi_mode_set()
986 	clk_prepare_enable(dsi->pclk);  in dw_mipi_dsi_mode_set()
988 	ret = phy_ops->get_lane_mbps(priv_data, adjusted_mode, dsi->mode_flags,  in dw_mipi_dsi_mode_set()
989 				     lanes, dsi->format, &dsi->lane_mbps);  in dw_mipi_dsi_mode_set()
993 	pm_runtime_get_sync(dsi->dev);  in dw_mipi_dsi_mode_set()
1009 	ret = phy_ops->init(priv_data);  in dw_mipi_dsi_mode_set()
1017 	/* Switch to cmd mode for panel-bridge pre_enable & panel prepare */  in dw_mipi_dsi_mode_set()
1020 	if (phy_ops->power_on)  in dw_mipi_dsi_mode_set()
1021 		phy_ops->power_on(dsi->plat_data->priv_data);  in dw_mipi_dsi_mode_set()
1030 	dw_mipi_dsi_mode_set(dsi, &dsi->mode);  in dw_mipi_dsi_bridge_atomic_pre_enable()
1031 	if (dsi->slave)  in dw_mipi_dsi_bridge_atomic_pre_enable()
1032 		dw_mipi_dsi_mode_set(dsi->slave, &dsi->mode);  in dw_mipi_dsi_bridge_atomic_pre_enable()
1042 	drm_mode_copy(&dsi->mode, adjusted_mode);  in dw_mipi_dsi_bridge_mode_set()
1050 	/* Switch to video mode for panel-bridge enable & panel enable */  in dw_mipi_dsi_bridge_atomic_enable()
1052 	if (dsi->slave)  in dw_mipi_dsi_bridge_atomic_enable()
1053 		dw_mipi_dsi_set_mode(dsi->slave, MIPI_DSI_MODE_VIDEO);  in dw_mipi_dsi_bridge_atomic_enable()
1062 	const struct dw_mipi_dsi_plat_data *pdata = dsi->plat_data;  in dw_mipi_dsi_bridge_mode_valid()
1065 	if (pdata->mode_valid)  in dw_mipi_dsi_bridge_mode_valid()
1066 		mode_status = pdata->mode_valid(pdata->priv_data, mode,  in dw_mipi_dsi_bridge_mode_valid()
1067 						dsi->mode_flags,  in dw_mipi_dsi_bridge_mode_valid()
1069 						dsi->format);  in dw_mipi_dsi_bridge_mode_valid()
1080 	bridge->encoder->encoder_type = DRM_MODE_ENCODER_DSI;  in dw_mipi_dsi_bridge_attach()
1082 	/* Attach the panel-bridge to the dsi bridge */  in dw_mipi_dsi_bridge_attach()
1083 	return drm_bridge_attach(bridge->encoder, dsi->panel_bridge, bridge,  in dw_mipi_dsi_bridge_attach()
1110 		return -ENODEV;  in dw_mipi_dsi_debugfs_write()
1112 	dsi = vpg->dsi;  in dw_mipi_dsi_debugfs_write()
1114 	*vpg->reg = (bool)val;  in dw_mipi_dsi_debugfs_write()
1118 	if (*vpg->reg)  in dw_mipi_dsi_debugfs_write()
1119 		mode_cfg |= vpg->mask;  in dw_mipi_dsi_debugfs_write()
1121 		mode_cfg &= ~vpg->mask;  in dw_mipi_dsi_debugfs_write()
1133 		return -ENODEV;  in dw_mipi_dsi_debugfs_show()
1135 	*val = *vpg->reg;  in dw_mipi_dsi_debugfs_show()
1153 	dsi->debugfs_vpg = kmemdup(debugfs, sizeof(debugfs), GFP_KERNEL);  in debugfs_create_files()
1154 	if (!dsi->debugfs_vpg)  in debugfs_create_files()
1158 		debugfs_create_file(dsi->debugfs_vpg[i].name, 0644,  in debugfs_create_files()
1159 				    dsi->debugfs, &dsi->debugfs_vpg[i],  in debugfs_create_files()
1165 	dsi->debugfs = debugfs_create_dir(dev_name(dsi->dev), NULL);  in dw_mipi_dsi_debugfs_init()
1166 	if (IS_ERR(dsi->debugfs)) {  in dw_mipi_dsi_debugfs_init()
1167 		dev_err(dsi->dev, "failed to create debugfs root\n");  in dw_mipi_dsi_debugfs_init()
1176 	debugfs_remove_recursive(dsi->debugfs);  in dw_mipi_dsi_debugfs_remove()
1177 	kfree(dsi->debugfs_vpg);  in dw_mipi_dsi_debugfs_remove()
1191 	struct device *dev = &pdev->dev;  in __dw_mipi_dsi_probe()
1198 		return ERR_PTR(-ENOMEM);  in __dw_mipi_dsi_probe()
1200 	dsi->dev = dev;  in __dw_mipi_dsi_probe()
1201 	dsi->plat_data = plat_data;  in __dw_mipi_dsi_probe()
1203 	if (!plat_data->phy_ops->init || !plat_data->phy_ops->get_lane_mbps ||  in __dw_mipi_dsi_probe()
1204 	    !plat_data->phy_ops->get_timing) {  in __dw_mipi_dsi_probe()
1206 		return ERR_PTR(-ENODEV);  in __dw_mipi_dsi_probe()
1209 	if (!plat_data->base) {  in __dw_mipi_dsi_probe()
1210 		dsi->base = devm_platform_ioremap_resource(pdev, 0);  in __dw_mipi_dsi_probe()
1211 		if (IS_ERR(dsi->base))  in __dw_mipi_dsi_probe()
1212 			return ERR_PTR(-ENODEV);  in __dw_mipi_dsi_probe()
1215 		dsi->base = plat_data->base;  in __dw_mipi_dsi_probe()
1218 	dsi->pclk = devm_clk_get(dev, "pclk");  in __dw_mipi_dsi_probe()
1219 	if (IS_ERR(dsi->pclk)) {  in __dw_mipi_dsi_probe()
1220 		ret = PTR_ERR(dsi->pclk);  in __dw_mipi_dsi_probe()
1233 		if (ret != -EPROBE_DEFER)  in __dw_mipi_dsi_probe()
1240 		ret = clk_prepare_enable(dsi->pclk);  in __dw_mipi_dsi_probe()
1250 		clk_disable_unprepare(dsi->pclk);  in __dw_mipi_dsi_probe()
1256 	dsi->dsi_host.ops = &dw_mipi_dsi_host_ops;  in __dw_mipi_dsi_probe()
1257 	dsi->dsi_host.dev = dev;  in __dw_mipi_dsi_probe()
1258 	ret = mipi_dsi_host_register(&dsi->dsi_host);  in __dw_mipi_dsi_probe()
1266 	dsi->bridge.driver_private = dsi;  in __dw_mipi_dsi_probe()
1267 	dsi->bridge.funcs = &dw_mipi_dsi_bridge_funcs;  in __dw_mipi_dsi_probe()
1268 	dsi->bridge.of_node = pdev->dev.of_node;  in __dw_mipi_dsi_probe()
1275 	mipi_dsi_host_unregister(&dsi->dsi_host);  in __dw_mipi_dsi_remove()
1277 	pm_runtime_disable(dsi->dev);  in __dw_mipi_dsi_remove()
1284 	dsi->slave = slave;  in dw_mipi_dsi_set_slave()
1285 	dsi->slave->master = dsi;  in dw_mipi_dsi_set_slave()
1288 	dsi->slave->lanes = dsi->lanes;  in dw_mipi_dsi_set_slave()
1289 	dsi->slave->channel = dsi->channel;  in dw_mipi_dsi_set_slave()
1290 	dsi->slave->format = dsi->format;  in dw_mipi_dsi_set_slave()
1291 	dsi->slave->mode_flags = dsi->mode_flags;  in dw_mipi_dsi_set_slave()
1297 	return &dsi->bridge;  in dw_mipi_dsi_get_bridge()
1323 	return drm_bridge_attach(encoder, &dsi->bridge, NULL, 0);  in dw_mipi_dsi_bind()
1332 MODULE_AUTHOR("Chris Zhong <zyw@rock-chips.com>");
1336 MODULE_ALIAS("platform:dw-mipi-dsi");