Lines Matching +full:dual +full:- +full:lane
72 drm_err(&dev_priv->drm, "DSI header credits not released\n"); in wait_for_header_credits()
84 drm_err(&dev_priv->drm, "DSI payload credits not released\n"); in wait_for_payload_credits()
101 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in wait_for_cmds_dispatched_to_panel()
109 for_each_dsi_port(port, intel_dsi->ports) { in wait_for_cmds_dispatched_to_panel()
116 for_each_dsi_port(port, intel_dsi->ports) { in wait_for_cmds_dispatched_to_panel()
117 dsi = intel_dsi->dsi_hosts[port]->device; in wait_for_cmds_dispatched_to_panel()
118 dsi->mode_flags |= MIPI_DSI_MODE_LPM; in wait_for_cmds_dispatched_to_panel()
119 dsi->channel = 0; in wait_for_cmds_dispatched_to_panel()
122 drm_err(&dev_priv->drm, in wait_for_cmds_dispatched_to_panel()
127 for_each_dsi_port(port, intel_dsi->ports) { in wait_for_cmds_dispatched_to_panel()
133 for_each_dsi_port(port, intel_dsi->ports) { in wait_for_cmds_dispatched_to_panel()
137 drm_err(&dev_priv->drm, "LPTX bit not cleared\n"); in wait_for_cmds_dispatched_to_panel()
144 struct intel_dsi *intel_dsi = host->intel_dsi; in dsi_send_pkt_payld()
145 struct drm_i915_private *i915 = to_i915(intel_dsi->base.base.dev); in dsi_send_pkt_payld()
146 enum transcoder dsi_trans = dsi_port_to_transcoder(host->port); in dsi_send_pkt_payld()
147 const u8 *data = packet->payload; in dsi_send_pkt_payld()
148 u32 len = packet->payload_length; in dsi_send_pkt_payld()
153 drm_err(&i915->drm, "payload size exceeds max queue limit\n"); in dsi_send_pkt_payld()
154 return -EINVAL; in dsi_send_pkt_payld()
161 return -EBUSY; in dsi_send_pkt_payld()
163 for (j = 0; j < min_t(u32, len - i, 4); j++) in dsi_send_pkt_payld()
176 struct intel_dsi *intel_dsi = host->intel_dsi; in dsi_send_pkt_hdr()
177 struct drm_i915_private *dev_priv = to_i915(intel_dsi->base.base.dev); in dsi_send_pkt_hdr()
178 enum transcoder dsi_trans = dsi_port_to_transcoder(host->port); in dsi_send_pkt_hdr()
182 return -EBUSY; in dsi_send_pkt_hdr()
186 if (packet->payload) in dsi_send_pkt_hdr()
199 tmp |= ((packet->header[0] & VC_MASK) << VC_SHIFT); in dsi_send_pkt_hdr()
200 tmp |= ((packet->header[0] & DT_MASK) << DT_SHIFT); in dsi_send_pkt_hdr()
201 tmp |= (packet->header[1] << PARAM_WC_LOWER_SHIFT); in dsi_send_pkt_hdr()
202 tmp |= (packet->header[2] << PARAM_WC_UPPER_SHIFT); in dsi_send_pkt_hdr()
210 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in icl_dsi_frame_update()
211 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in icl_dsi_frame_update()
215 mode_flags = crtc_state->mode_flags; in icl_dsi_frame_update()
218 * case 1 also covers dual link in icl_dsi_frame_update()
219 * In case of dual link, frame update should be set on in icl_dsi_frame_update()
234 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in dsi_program_swing_and_deemphasis()
238 int lane; in dsi_program_swing_and_deemphasis() local
240 for_each_dsi_phy(phy, intel_dsi->phys) { in dsi_program_swing_and_deemphasis()
242 * Program voltage swing and pre-emphasis level values as per in dsi_program_swing_and_deemphasis()
271 for (lane = 0; lane <= 3; lane++) in dsi_program_swing_and_deemphasis()
272 intel_de_rmw(dev_priv, ICL_PORT_TX_DW4_LN(lane, phy), in dsi_program_swing_and_deemphasis()
280 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in configure_dual_link_mode()
287 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); in configure_dual_link_mode()
289 dss_ctl1_reg = ICL_PIPE_DSS_CTL1(crtc->pipe); in configure_dual_link_mode()
290 dss_ctl2_reg = ICL_PIPE_DSS_CTL2(crtc->pipe); in configure_dual_link_mode()
299 dss_ctl1 |= OVERLAP_PIXELS(intel_dsi->pixel_overlap); in configure_dual_link_mode()
301 if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) { in configure_dual_link_mode()
303 &pipe_config->hw.adjusted_mode; in configure_dual_link_mode()
304 u16 hactive = adjusted_mode->crtc_hdisplay; in configure_dual_link_mode()
308 dl_buffer_depth = hactive / 2 + intel_dsi->pixel_overlap; in configure_dual_link_mode()
311 drm_err(&dev_priv->drm, in configure_dual_link_mode()
333 if (crtc_state->dsc.compression_enable) in afe_clk()
334 bpp = fxp_q4_to_int(crtc_state->dsc.compressed_bpp_x16); in afe_clk()
336 bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format); in afe_clk()
338 return DIV_ROUND_CLOSEST(intel_dsi->pclk * bpp, intel_dsi->lane_count); in afe_clk()
344 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in gen11_dsi_program_esc_clk_div()
357 esc_clk_div_m_phy = (act_word_clk - 1) / 2; in gen11_dsi_program_esc_clk_div()
362 for_each_dsi_port(port, intel_dsi->ports) { in gen11_dsi_program_esc_clk_div()
368 for_each_dsi_port(port, intel_dsi->ports) { in gen11_dsi_program_esc_clk_div()
375 for_each_dsi_port(port, intel_dsi->ports) { in gen11_dsi_program_esc_clk_div()
388 for_each_dsi_port(port, intel_dsi->ports) { in get_dsi_io_power_domains()
389 drm_WARN_ON(&dev_priv->drm, intel_dsi->io_wakeref[port]); in get_dsi_io_power_domains()
390 intel_dsi->io_wakeref[port] = in get_dsi_io_power_domains()
400 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in gen11_dsi_enable_io_power()
404 for_each_dsi_port(port, intel_dsi->ports) in gen11_dsi_enable_io_power()
413 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in gen11_dsi_power_up_lanes()
417 for_each_dsi_phy(phy, intel_dsi->phys) in gen11_dsi_power_up_lanes()
419 intel_dsi->lane_count, false); in gen11_dsi_power_up_lanes()
424 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in gen11_dsi_config_phy_lanes_sequence()
428 int lane; in gen11_dsi_config_phy_lanes_sequence() local
431 for_each_dsi_phy(phy, intel_dsi->phys) { in gen11_dsi_config_phy_lanes_sequence()
433 for (lane = 0; lane <= 3; lane++) in gen11_dsi_config_phy_lanes_sequence()
434 intel_de_rmw(dev_priv, ICL_PORT_TX_DW4_LN(lane, phy), in gen11_dsi_config_phy_lanes_sequence()
435 LOADGEN_SELECT, lane != 2 ? LOADGEN_SELECT : 0); in gen11_dsi_config_phy_lanes_sequence()
439 for_each_dsi_phy(phy, intel_dsi->phys) { in gen11_dsi_config_phy_lanes_sequence()
466 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in gen11_dsi_voltage_swing_program_seq()
472 for_each_dsi_phy(phy, intel_dsi->phys) { in gen11_dsi_voltage_swing_program_seq()
482 * as part of lane phy sequence configuration in gen11_dsi_voltage_swing_program_seq()
484 for_each_dsi_phy(phy, intel_dsi->phys) in gen11_dsi_voltage_swing_program_seq()
488 for_each_dsi_phy(phy, intel_dsi->phys) { in gen11_dsi_voltage_swing_program_seq()
495 /* Program swing and de-emphasis */ in gen11_dsi_voltage_swing_program_seq()
499 for_each_dsi_phy(phy, intel_dsi->phys) { in gen11_dsi_voltage_swing_program_seq()
509 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in gen11_dsi_enable_ddi_buffer()
513 for_each_dsi_port(port, intel_dsi->ports) { in gen11_dsi_enable_ddi_buffer()
519 drm_err(&dev_priv->drm, "DDI port:%c buffer idle\n", in gen11_dsi_enable_ddi_buffer()
528 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in gen11_dsi_setup_dphy_timings()
534 for_each_dsi_port(port, intel_dsi->ports) in gen11_dsi_setup_dphy_timings()
536 intel_dsi->dphy_reg); in gen11_dsi_setup_dphy_timings()
539 for_each_dsi_port(port, intel_dsi->ports) in gen11_dsi_setup_dphy_timings()
541 intel_dsi->dphy_data_lane_reg); in gen11_dsi_setup_dphy_timings()
551 for_each_dsi_port(port, intel_dsi->ports) in gen11_dsi_setup_dphy_timings()
559 for_each_dsi_phy(phy, intel_dsi->phys) in gen11_dsi_setup_dphy_timings()
569 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in gen11_dsi_setup_timings()
573 /* Program T-INIT master registers */ in gen11_dsi_setup_timings()
574 for_each_dsi_port(port, intel_dsi->ports) in gen11_dsi_setup_timings()
576 DSI_T_INIT_MASTER_MASK, intel_dsi->init_count); in gen11_dsi_setup_timings()
579 for_each_dsi_port(port, intel_dsi->ports) in gen11_dsi_setup_timings()
581 intel_dsi->dphy_reg); in gen11_dsi_setup_timings()
584 for_each_dsi_port(port, intel_dsi->ports) in gen11_dsi_setup_timings()
586 intel_dsi->dphy_data_lane_reg); in gen11_dsi_setup_timings()
591 for_each_dsi_port(port, intel_dsi->ports) { in gen11_dsi_setup_timings()
602 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in gen11_dsi_gate_clocks()
607 mutex_lock(&dev_priv->display.dpll.lock); in gen11_dsi_gate_clocks()
609 for_each_dsi_phy(phy, intel_dsi->phys) in gen11_dsi_gate_clocks()
613 mutex_unlock(&dev_priv->display.dpll.lock); in gen11_dsi_gate_clocks()
618 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in gen11_dsi_ungate_clocks()
623 mutex_lock(&dev_priv->display.dpll.lock); in gen11_dsi_ungate_clocks()
625 for_each_dsi_phy(phy, intel_dsi->phys) in gen11_dsi_ungate_clocks()
629 mutex_unlock(&dev_priv->display.dpll.lock); in gen11_dsi_ungate_clocks()
634 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in gen11_dsi_is_clock_enabled()
642 for_each_dsi_phy(phy, intel_dsi->phys) { in gen11_dsi_is_clock_enabled()
653 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in gen11_dsi_map_pll()
655 struct intel_shared_dpll *pll = crtc_state->shared_dpll; in gen11_dsi_map_pll()
659 mutex_lock(&dev_priv->display.dpll.lock); in gen11_dsi_map_pll()
662 for_each_dsi_phy(phy, intel_dsi->phys) { in gen11_dsi_map_pll()
664 val |= ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy); in gen11_dsi_map_pll()
668 for_each_dsi_phy(phy, intel_dsi->phys) { in gen11_dsi_map_pll()
675 mutex_unlock(&dev_priv->display.dpll.lock); in gen11_dsi_map_pll()
682 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in gen11_dsi_configure_transcoder()
684 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); in gen11_dsi_configure_transcoder()
685 enum pipe pipe = crtc->pipe; in gen11_dsi_configure_transcoder()
690 for_each_dsi_port(port, intel_dsi->ports) { in gen11_dsi_configure_transcoder()
694 if (intel_dsi->eotp_pkt) in gen11_dsi_configure_transcoder()
707 if (intel_dsi->clock_stop) in gen11_dsi_configure_transcoder()
721 if (intel_dsi->bgr_enabled) in gen11_dsi_configure_transcoder()
726 if (pipe_config->dsc.compression_enable) { in gen11_dsi_configure_transcoder()
729 switch (intel_dsi->pixel_format) { in gen11_dsi_configure_transcoder()
731 MISSING_CASE(intel_dsi->pixel_format); in gen11_dsi_configure_transcoder()
756 switch (intel_dsi->video_mode) { in gen11_dsi_configure_transcoder()
758 MISSING_CASE(intel_dsi->video_mode); in gen11_dsi_configure_transcoder()
784 /* enable port sync mode if dual link */ in gen11_dsi_configure_transcoder()
785 if (intel_dsi->dual_link) { in gen11_dsi_configure_transcoder()
786 for_each_dsi_port(port, intel_dsi->ports) { in gen11_dsi_configure_transcoder()
797 for_each_dsi_port(port, intel_dsi->ports) { in gen11_dsi_configure_transcoder()
800 /* select data lane width */ in gen11_dsi_configure_transcoder()
804 tmp |= DDI_PORT_WIDTH(intel_dsi->lane_count); in gen11_dsi_configure_transcoder()
833 for_each_dsi_port(port, intel_dsi->ports) { in gen11_dsi_configure_transcoder()
837 drm_err(&dev_priv->drm, "DSI link not ready\n"); in gen11_dsi_configure_transcoder()
845 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in gen11_dsi_set_transcoder_timings()
848 &crtc_state->hw.adjusted_mode; in gen11_dsi_set_transcoder_timings()
863 * non-compressed link speeds, and simplifies down to the ratio between in gen11_dsi_set_transcoder_timings()
864 * compressed and non-compressed bpp. in gen11_dsi_set_transcoder_timings()
866 if (crtc_state->dsc.compression_enable) { in gen11_dsi_set_transcoder_timings()
867 mul = fxp_q4_to_int(crtc_state->dsc.compressed_bpp_x16); in gen11_dsi_set_transcoder_timings()
868 div = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format); in gen11_dsi_set_transcoder_timings()
871 hactive = adjusted_mode->crtc_hdisplay; in gen11_dsi_set_transcoder_timings()
874 htotal = DIV_ROUND_UP(adjusted_mode->crtc_htotal * mul, div); in gen11_dsi_set_transcoder_timings()
878 hsync_start = DIV_ROUND_UP(adjusted_mode->crtc_hsync_start * mul, div); in gen11_dsi_set_transcoder_timings()
879 hsync_end = DIV_ROUND_UP(adjusted_mode->crtc_hsync_end * mul, div); in gen11_dsi_set_transcoder_timings()
880 hsync_size = hsync_end - hsync_start; in gen11_dsi_set_transcoder_timings()
881 hback_porch = (adjusted_mode->crtc_htotal - in gen11_dsi_set_transcoder_timings()
882 adjusted_mode->crtc_hsync_end); in gen11_dsi_set_transcoder_timings()
883 vactive = adjusted_mode->crtc_vdisplay; in gen11_dsi_set_transcoder_timings()
886 vtotal = adjusted_mode->crtc_vtotal; in gen11_dsi_set_transcoder_timings()
890 if (crtc_state->dsc.compression_enable) in gen11_dsi_set_transcoder_timings()
891 bpp = fxp_q4_to_int(crtc_state->dsc.compressed_bpp_x16); in gen11_dsi_set_transcoder_timings()
893 bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format); in gen11_dsi_set_transcoder_timings()
896 line_time_us = (htotal * (bpp / 8) * byte_clk_period_ns) / (1000 * intel_dsi->lane_count); in gen11_dsi_set_transcoder_timings()
899 vsync_start = adjusted_mode->crtc_vsync_start; in gen11_dsi_set_transcoder_timings()
900 vsync_end = adjusted_mode->crtc_vsync_end; in gen11_dsi_set_transcoder_timings()
901 vsync_shift = hsync_start - htotal / 2; in gen11_dsi_set_transcoder_timings()
903 if (intel_dsi->dual_link) { in gen11_dsi_set_transcoder_timings()
905 if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) in gen11_dsi_set_transcoder_timings()
906 hactive += intel_dsi->pixel_overlap; in gen11_dsi_set_transcoder_timings()
911 if (adjusted_mode->crtc_hdisplay < 256) in gen11_dsi_set_transcoder_timings()
912 drm_err(&dev_priv->drm, "hactive is less then 256 pixels\n"); in gen11_dsi_set_transcoder_timings()
915 if (intel_dsi->pixel_format == MIPI_DSI_FMT_RGB666 && hactive % 4 != 0) in gen11_dsi_set_transcoder_timings()
916 drm_err(&dev_priv->drm, in gen11_dsi_set_transcoder_timings()
920 for_each_dsi_port(port, intel_dsi->ports) { in gen11_dsi_set_transcoder_timings()
923 HACTIVE(hactive - 1) | HTOTAL(htotal - 1)); in gen11_dsi_set_transcoder_timings()
928 if (intel_dsi->video_mode == NON_BURST_SYNC_PULSE) { in gen11_dsi_set_transcoder_timings()
931 drm_err(&dev_priv->drm, in gen11_dsi_set_transcoder_timings()
936 drm_err(&dev_priv->drm, "hback porch < 16 pixels\n"); in gen11_dsi_set_transcoder_timings()
938 if (intel_dsi->dual_link) { in gen11_dsi_set_transcoder_timings()
943 for_each_dsi_port(port, intel_dsi->ports) { in gen11_dsi_set_transcoder_timings()
947 HSYNC_START(hsync_start - 1) | HSYNC_END(hsync_end - 1)); in gen11_dsi_set_transcoder_timings()
952 for_each_dsi_port(port, intel_dsi->ports) { in gen11_dsi_set_transcoder_timings()
956 * non-interlaced info from VBT is not saved inside in gen11_dsi_set_transcoder_timings()
961 VACTIVE(vactive - 1) | VTOTAL(vtotal - 1)); in gen11_dsi_set_transcoder_timings()
965 drm_err(&dev_priv->drm, "Invalid vsync_end value\n"); in gen11_dsi_set_transcoder_timings()
968 drm_err(&dev_priv->drm, "vsync_start less than vactive\n"); in gen11_dsi_set_transcoder_timings()
972 for_each_dsi_port(port, intel_dsi->ports) { in gen11_dsi_set_transcoder_timings()
976 VSYNC_START(vsync_start - 1) | VSYNC_END(vsync_end - 1)); in gen11_dsi_set_transcoder_timings()
987 for_each_dsi_port(port, intel_dsi->ports) { in gen11_dsi_set_transcoder_timings()
1002 for_each_dsi_port(port, intel_dsi->ports) { in gen11_dsi_set_transcoder_timings()
1006 VBLANK_START(vactive - 1) | VBLANK_END(vtotal - 1)); in gen11_dsi_set_transcoder_timings()
1013 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in gen11_dsi_enable_transcoder()
1018 for_each_dsi_port(port, intel_dsi->ports) { in gen11_dsi_enable_transcoder()
1026 drm_err(&dev_priv->drm, in gen11_dsi_enable_transcoder()
1034 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in gen11_dsi_setup_timeouts()
1049 hs_tx_timeout = DIV_ROUND_UP(intel_dsi->hs_tx_timeout * mul, in gen11_dsi_setup_timeouts()
1051 lp_rx_timeout = DIV_ROUND_UP(intel_dsi->lp_rx_timeout * mul, divisor); in gen11_dsi_setup_timeouts()
1052 ta_timeout = DIV_ROUND_UP(intel_dsi->turn_arnd_val * mul, divisor); in gen11_dsi_setup_timeouts()
1054 for_each_dsi_port(port, intel_dsi->ports) { in gen11_dsi_setup_timeouts()
1081 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in gen11_dsi_config_util_pin()
1087 * for dual link/DSI1 TE is from slave DSI1 in gen11_dsi_config_util_pin()
1090 if (is_vid_mode(intel_dsi) || (intel_dsi->ports & BIT(PORT_B))) in gen11_dsi_config_util_pin()
1111 /* step 4b: configure lane sequencing of the Combo-PHY transmitters */ in gen11_dsi_enable_port_and_phy()
1117 /* setup D-PHY timings */ in gen11_dsi_enable_port_and_phy()
1139 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in gen11_dsi_powerup_panel()
1148 for_each_dsi_port(port, intel_dsi->ports) { in gen11_dsi_powerup_panel()
1159 dsi = intel_dsi->dsi_hosts[port]->device; in gen11_dsi_powerup_panel()
1162 drm_err(&dev_priv->drm, in gen11_dsi_powerup_panel()
1182 msleep(intel_dsi->panel_on_delay); in gen11_dsi_pre_pll_enable()
1222 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in icl_apply_kvmr_pipe_a_wa()
1231 * Wa_16012360555:adl-p
1238 struct drm_i915_private *i915 = to_i915(encoder->base.dev); in adlp_set_lp_hs_wakeup_gb()
1243 for_each_dsi_port(port, intel_dsi->ports) in adlp_set_lp_hs_wakeup_gb()
1256 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in gen11_dsi_enable()
1259 icl_apply_kvmr_pipe_a_wa(encoder, crtc->pipe, true); in gen11_dsi_enable()
1261 /* Wa_16012360555:adl-p */ in gen11_dsi_enable()
1278 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in gen11_dsi_disable_transcoder()
1283 for_each_dsi_port(port, intel_dsi->ports) { in gen11_dsi_disable_transcoder()
1293 drm_err(&dev_priv->drm, in gen11_dsi_disable_transcoder()
1310 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in gen11_dsi_deconfigure_trancoder()
1318 for_each_dsi_port(port, intel_dsi->ports) in gen11_dsi_deconfigure_trancoder()
1324 for_each_dsi_port(port, intel_dsi->ports) { in gen11_dsi_deconfigure_trancoder()
1334 drm_err(&dev_priv->drm, "DSI link not in ULPS\n"); in gen11_dsi_deconfigure_trancoder()
1338 for_each_dsi_port(port, intel_dsi->ports) { in gen11_dsi_deconfigure_trancoder()
1345 /* disable port sync mode if dual link */ in gen11_dsi_deconfigure_trancoder()
1346 if (intel_dsi->dual_link) { in gen11_dsi_deconfigure_trancoder()
1347 for_each_dsi_port(port, intel_dsi->ports) { in gen11_dsi_deconfigure_trancoder()
1358 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in gen11_dsi_disable_port()
1363 for_each_dsi_port(port, intel_dsi->ports) { in gen11_dsi_disable_port()
1369 drm_err(&dev_priv->drm, in gen11_dsi_disable_port()
1378 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in gen11_dsi_disable_io_power()
1382 for_each_dsi_port(port, intel_dsi->ports) { in gen11_dsi_disable_io_power()
1385 wakeref = fetch_and_zero(&intel_dsi->io_wakeref[port]); in gen11_dsi_disable_io_power()
1394 for_each_dsi_port(port, intel_dsi->ports) in gen11_dsi_disable_io_power()
1417 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc); in gen11_dsi_post_disable()
1425 icl_apply_kvmr_pipe_a_wa(encoder, crtc->pipe, false); in gen11_dsi_post_disable()
1446 msleep(intel_dsi->panel_off_delay); in gen11_dsi_post_disable()
1449 intel_dsi->panel_power_off_time = ktime_get_boottime(); in gen11_dsi_post_disable()
1455 struct drm_i915_private *i915 = to_i915(connector->dev); in gen11_dsi_mode_valid()
1471 &pipe_config->hw.adjusted_mode; in gen11_dsi_get_timings()
1473 if (pipe_config->dsc.compressed_bpp_x16) { in gen11_dsi_get_timings()
1474 int div = fxp_q4_to_int(pipe_config->dsc.compressed_bpp_x16); in gen11_dsi_get_timings()
1475 int mul = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format); in gen11_dsi_get_timings()
1477 adjusted_mode->crtc_htotal = in gen11_dsi_get_timings()
1478 DIV_ROUND_UP(adjusted_mode->crtc_htotal * mul, div); in gen11_dsi_get_timings()
1479 adjusted_mode->crtc_hsync_start = in gen11_dsi_get_timings()
1480 DIV_ROUND_UP(adjusted_mode->crtc_hsync_start * mul, div); in gen11_dsi_get_timings()
1481 adjusted_mode->crtc_hsync_end = in gen11_dsi_get_timings()
1482 DIV_ROUND_UP(adjusted_mode->crtc_hsync_end * mul, div); in gen11_dsi_get_timings()
1485 if (intel_dsi->dual_link) { in gen11_dsi_get_timings()
1486 adjusted_mode->crtc_hdisplay *= 2; in gen11_dsi_get_timings()
1487 if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) in gen11_dsi_get_timings()
1488 adjusted_mode->crtc_hdisplay -= in gen11_dsi_get_timings()
1489 intel_dsi->pixel_overlap; in gen11_dsi_get_timings()
1490 adjusted_mode->crtc_htotal *= 2; in gen11_dsi_get_timings()
1492 adjusted_mode->crtc_hblank_start = adjusted_mode->crtc_hdisplay; in gen11_dsi_get_timings()
1493 adjusted_mode->crtc_hblank_end = adjusted_mode->crtc_htotal; in gen11_dsi_get_timings()
1495 if (intel_dsi->operation_mode == INTEL_DSI_VIDEO_MODE) { in gen11_dsi_get_timings()
1496 if (intel_dsi->dual_link) { in gen11_dsi_get_timings()
1497 adjusted_mode->crtc_hsync_start *= 2; in gen11_dsi_get_timings()
1498 adjusted_mode->crtc_hsync_end *= 2; in gen11_dsi_get_timings()
1501 adjusted_mode->crtc_vblank_start = adjusted_mode->crtc_vdisplay; in gen11_dsi_get_timings()
1502 adjusted_mode->crtc_vblank_end = adjusted_mode->crtc_vtotal; in gen11_dsi_get_timings()
1507 struct drm_device *dev = intel_dsi->base.base.dev; in gen11_dsi_is_periodic_cmd_mode()
1512 if (intel_dsi->ports == BIT(PORT_B)) in gen11_dsi_is_periodic_cmd_mode()
1524 if (intel_dsi->ports == (BIT(PORT_B) | BIT(PORT_A))) in gen11_dsi_get_cmd_mode_config()
1525 pipe_config->mode_flags |= I915_MODE_FLAG_DSI_USE_TE1 | in gen11_dsi_get_cmd_mode_config()
1527 else if (intel_dsi->ports == BIT(PORT_B)) in gen11_dsi_get_cmd_mode_config()
1528 pipe_config->mode_flags |= I915_MODE_FLAG_DSI_USE_TE1; in gen11_dsi_get_cmd_mode_config()
1530 pipe_config->mode_flags |= I915_MODE_FLAG_DSI_USE_TE0; in gen11_dsi_get_cmd_mode_config()
1536 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); in gen11_dsi_get_config()
1541 pipe_config->hw.adjusted_mode.crtc_clock = intel_dsi->pclk; in gen11_dsi_get_config()
1542 if (intel_dsi->dual_link) in gen11_dsi_get_config()
1543 pipe_config->hw.adjusted_mode.crtc_clock *= 2; in gen11_dsi_get_config()
1546 pipe_config->output_types |= BIT(INTEL_OUTPUT_DSI); in gen11_dsi_get_config()
1547 pipe_config->pipe_bpp = bdw_get_pipe_misc_bpp(crtc); in gen11_dsi_get_config()
1554 pipe_config->mode_flags |= I915_MODE_FLAG_DSI_PERIODIC_CMD_MODE; in gen11_dsi_get_config()
1560 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in gen11_dsi_sync_state()
1567 intel_crtc = to_intel_crtc(crtc_state->uapi.crtc); in gen11_dsi_sync_state()
1568 pipe = intel_crtc->pipe; in gen11_dsi_sync_state()
1573 drm_dbg_kms(&dev_priv->drm, in gen11_dsi_sync_state()
1575 encoder->base.base.id, in gen11_dsi_sync_state()
1576 encoder->base.name); in gen11_dsi_sync_state()
1582 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in gen11_dsi_dsc_compute_config()
1583 struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config; in gen11_dsi_dsc_compute_config()
1592 if (crtc_state->pipe_bpp < 8 * 3) in gen11_dsi_dsc_compute_config()
1593 return -EINVAL; in gen11_dsi_dsc_compute_config()
1596 if (crtc_state->dsc.slice_count > 1) in gen11_dsi_dsc_compute_config()
1597 crtc_state->dsc.dsc_split = true; in gen11_dsi_dsc_compute_config()
1600 vdsc_cfg->rc_model_size = DSC_RC_MODEL_SIZE_CONST; in gen11_dsi_dsc_compute_config()
1602 vdsc_cfg->pic_height = crtc_state->hw.adjusted_mode.crtc_vdisplay; in gen11_dsi_dsc_compute_config()
1609 drm_WARN_ON(&dev_priv->drm, vdsc_cfg->vbr_enable); in gen11_dsi_dsc_compute_config()
1610 drm_WARN_ON(&dev_priv->drm, vdsc_cfg->simple_422); in gen11_dsi_dsc_compute_config()
1611 drm_WARN_ON(&dev_priv->drm, in gen11_dsi_dsc_compute_config()
1612 vdsc_cfg->pic_width % vdsc_cfg->slice_width); in gen11_dsi_dsc_compute_config()
1613 drm_WARN_ON(&dev_priv->drm, vdsc_cfg->slice_height < 8); in gen11_dsi_dsc_compute_config()
1614 drm_WARN_ON(&dev_priv->drm, in gen11_dsi_dsc_compute_config()
1615 vdsc_cfg->pic_height % vdsc_cfg->slice_height); in gen11_dsi_dsc_compute_config()
1621 crtc_state->dsc.compression_enable = true; in gen11_dsi_dsc_compute_config()
1630 struct drm_i915_private *i915 = to_i915(encoder->base.dev); in gen11_dsi_compute_config()
1632 struct intel_connector *intel_connector = intel_dsi->attached_connector; in gen11_dsi_compute_config()
1634 &pipe_config->hw.adjusted_mode; in gen11_dsi_compute_config()
1637 pipe_config->sink_format = INTEL_OUTPUT_FORMAT_RGB; in gen11_dsi_compute_config()
1638 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB; in gen11_dsi_compute_config()
1648 adjusted_mode->flags = 0; in gen11_dsi_compute_config()
1650 /* Dual link goes to trancoder DSI'0' */ in gen11_dsi_compute_config()
1651 if (intel_dsi->ports == BIT(PORT_B)) in gen11_dsi_compute_config()
1652 pipe_config->cpu_transcoder = TRANSCODER_DSI_1; in gen11_dsi_compute_config()
1654 pipe_config->cpu_transcoder = TRANSCODER_DSI_0; in gen11_dsi_compute_config()
1656 if (intel_dsi->pixel_format == MIPI_DSI_FMT_RGB888) in gen11_dsi_compute_config()
1657 pipe_config->pipe_bpp = 24; in gen11_dsi_compute_config()
1659 pipe_config->pipe_bpp = 18; in gen11_dsi_compute_config()
1661 pipe_config->clock_set = true; in gen11_dsi_compute_config()
1664 drm_dbg_kms(&i915->drm, "Attempting to use DSC failed\n"); in gen11_dsi_compute_config()
1666 pipe_config->port_clock = afe_clk(encoder, pipe_config) / 5; in gen11_dsi_compute_config()
1671 * dual link is enabled in gen11_dsi_compute_config()
1682 struct drm_i915_private *i915 = to_i915(encoder->base.dev); in gen11_dsi_get_power_domains()
1691 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in gen11_dsi_get_hw_state()
1700 encoder->power_domain); in gen11_dsi_get_hw_state()
1704 for_each_dsi_port(port, intel_dsi->ports) { in gen11_dsi_get_hw_state()
1722 drm_err(&dev_priv->drm, "Invalid PIPE input\n"); in gen11_dsi_get_hw_state()
1730 intel_display_power_put(dev_priv, encoder->power_domain, wakeref); in gen11_dsi_get_hw_state()
1737 if (crtc_state->dsc.compression_enable) { in gen11_dsi_initial_fastset_check()
1738 drm_dbg_kms(encoder->base.dev, "Forcing full modeset due to DSC being enabled\n"); in gen11_dsi_initial_fastset_check()
1739 crtc_state->uapi.mode_changed = true; in gen11_dsi_initial_fastset_check()
1798 if (msg->flags & MIPI_DSI_MSG_USE_LPM) in gen11_dsi_host_transfer()
1802 if (mipi_dsi_packet_format_is_long(msg->type)) { in gen11_dsi_host_transfer()
1836 struct drm_device *dev = intel_dsi->base.base.dev; in icl_dphy_param_init()
1838 struct intel_connector *connector = intel_dsi->attached_connector; in icl_dphy_param_init()
1839 struct mipi_config *mipi_config = connector->panel.vbt.dsi.config; in icl_dphy_param_init()
1848 tclk_trail_ns = max(mipi_config->tclk_trail, mipi_config->ths_trail); in icl_dphy_param_init()
1849 ths_prepare_ns = max(mipi_config->ths_prepare, in icl_dphy_param_init()
1850 mipi_config->tclk_prepare); in icl_dphy_param_init()
1861 drm_dbg_kms(&dev_priv->drm, "prepare_cnt out of range (%d)\n", in icl_dphy_param_init()
1867 clk_zero_cnt = DIV_ROUND_UP(mipi_config->tclk_prepare_clkzero - in icl_dphy_param_init()
1870 drm_dbg_kms(&dev_priv->drm, in icl_dphy_param_init()
1878 drm_dbg_kms(&dev_priv->drm, "trail_cnt out of range (%d)\n", in icl_dphy_param_init()
1884 tclk_pre_cnt = DIV_ROUND_UP(mipi_config->tclk_pre, tlpx_ns); in icl_dphy_param_init()
1886 drm_dbg_kms(&dev_priv->drm, in icl_dphy_param_init()
1892 hs_zero_cnt = DIV_ROUND_UP(mipi_config->ths_prepare_hszero - in icl_dphy_param_init()
1895 drm_dbg_kms(&dev_priv->drm, "hs_zero_cnt out of range (%d)\n", in icl_dphy_param_init()
1901 exit_zero_cnt = DIV_ROUND_UP(mipi_config->ths_exit, tlpx_ns); in icl_dphy_param_init()
1903 drm_dbg_kms(&dev_priv->drm, in icl_dphy_param_init()
1909 /* clock lane dphy timings */ in icl_dphy_param_init()
1910 intel_dsi->dphy_reg = (CLK_PREPARE_OVERRIDE | in icl_dphy_param_init()
1920 intel_dsi->dphy_data_lane_reg = (HS_PREPARE_OVERRIDE | in icl_dphy_param_init()
1937 intel_attach_scaling_mode_property(&connector->base); in icl_dsi_add_properties()
1939 drm_connector_set_panel_orientation_with_quirk(&connector->base, in icl_dsi_add_properties()
1941 fixed_mode->hdisplay, in icl_dsi_add_properties()
1942 fixed_mode->vdisplay); in icl_dsi_add_properties()
1948 struct intel_display *display = &dev_priv->display; in icl_dsi_init()
1969 encoder = &intel_dsi->base; in icl_dsi_init()
1970 intel_dsi->attached_connector = intel_connector; in icl_dsi_init()
1971 connector = &intel_connector->base; in icl_dsi_init()
1973 encoder->devdata = devdata; in icl_dsi_init()
1976 drm_encoder_init(&dev_priv->drm, &encoder->base, &gen11_dsi_encoder_funcs, in icl_dsi_init()
1979 encoder->pre_pll_enable = gen11_dsi_pre_pll_enable; in icl_dsi_init()
1980 encoder->pre_enable = gen11_dsi_pre_enable; in icl_dsi_init()
1981 encoder->enable = gen11_dsi_enable; in icl_dsi_init()
1982 encoder->disable = gen11_dsi_disable; in icl_dsi_init()
1983 encoder->post_disable = gen11_dsi_post_disable; in icl_dsi_init()
1984 encoder->port = port; in icl_dsi_init()
1985 encoder->get_config = gen11_dsi_get_config; in icl_dsi_init()
1986 encoder->sync_state = gen11_dsi_sync_state; in icl_dsi_init()
1987 encoder->update_pipe = intel_backlight_update; in icl_dsi_init()
1988 encoder->compute_config = gen11_dsi_compute_config; in icl_dsi_init()
1989 encoder->get_hw_state = gen11_dsi_get_hw_state; in icl_dsi_init()
1990 encoder->initial_fastset_check = gen11_dsi_initial_fastset_check; in icl_dsi_init()
1991 encoder->type = INTEL_OUTPUT_DSI; in icl_dsi_init()
1992 encoder->cloneable = 0; in icl_dsi_init()
1993 encoder->pipe_mask = ~0; in icl_dsi_init()
1994 encoder->power_domain = POWER_DOMAIN_PORT_DSI; in icl_dsi_init()
1995 encoder->get_power_domains = gen11_dsi_get_power_domains; in icl_dsi_init()
1996 encoder->disable_clock = gen11_dsi_gate_clocks; in icl_dsi_init()
1997 encoder->is_clock_enabled = gen11_dsi_is_clock_enabled; in icl_dsi_init()
1998 encoder->shutdown = intel_dsi_shutdown; in icl_dsi_init()
2001 drm_connector_init(&dev_priv->drm, connector, &gen11_dsi_connector_funcs, in icl_dsi_init()
2004 connector->display_info.subpixel_order = SubPixelHorizontalRGB; in icl_dsi_init()
2005 intel_connector->get_hw_state = intel_connector_get_hw_state; in icl_dsi_init()
2010 intel_dsi->panel_power_off_time = ktime_get_boottime(); in icl_dsi_init()
2012 intel_bios_init_panel_late(display, &intel_connector->panel, encoder->devdata, NULL); in icl_dsi_init()
2014 mutex_lock(&dev_priv->drm.mode_config.mutex); in icl_dsi_init()
2016 mutex_unlock(&dev_priv->drm.mode_config.mutex); in icl_dsi_init()
2019 drm_err(&dev_priv->drm, "DSI fixed mode info missing\n"); in icl_dsi_init()
2027 if (intel_connector->panel.vbt.dsi.config->dual_link) in icl_dsi_init()
2028 intel_dsi->ports = BIT(PORT_A) | BIT(PORT_B); in icl_dsi_init()
2030 intel_dsi->ports = BIT(port); in icl_dsi_init()
2032 if (drm_WARN_ON(&dev_priv->drm, intel_connector->panel.vbt.dsi.bl_ports & ~intel_dsi->ports)) in icl_dsi_init()
2033 intel_connector->panel.vbt.dsi.bl_ports &= intel_dsi->ports; in icl_dsi_init()
2035 if (drm_WARN_ON(&dev_priv->drm, intel_connector->panel.vbt.dsi.cabc_ports & ~intel_dsi->ports)) in icl_dsi_init()
2036 intel_connector->panel.vbt.dsi.cabc_ports &= intel_dsi->ports; in icl_dsi_init()
2038 for_each_dsi_port(port, intel_dsi->ports) { in icl_dsi_init()
2045 intel_dsi->dsi_hosts[port] = host; in icl_dsi_init()
2049 drm_dbg_kms(&dev_priv->drm, "no device found\n"); in icl_dsi_init()
2060 drm_encoder_cleanup(&encoder->base); in icl_dsi_init()