| /linux-6.12.1/drivers/clk/ti/ |
| D | divider.c | 3 * TI Divider Clock
32 static void _setup_mask(struct clk_omap_divider *divider) in _setup_mask() argument
38 if (divider->table) { in _setup_mask()
41 for (clkt = divider->table; clkt->div; clkt++) in _setup_mask()
45 max_val = divider->max; in _setup_mask()
47 if (!(divider->flags & CLK_DIVIDER_ONE_BASED) && in _setup_mask()
48 !(divider->flags & CLK_DIVIDER_POWER_OF_TWO)) in _setup_mask()
52 if (divider->flags & CLK_DIVIDER_POWER_OF_TWO) in _setup_mask()
57 divider->mask = (1 << fls(mask)) - 1; in _setup_mask()
60 static unsigned int _get_div(struct clk_omap_divider *divider, unsigned int val) in _get_div() argument
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| /linux-6.12.1/drivers/clk/tegra/ |
| D | clk-divider.c | 21 static int get_div(struct tegra_clk_frac_div *divider, unsigned long rate, in get_div() argument
26 div = div_frac_get(rate, parent_rate, divider->width, in get_div()
27 divider->frac_width, divider->flags); in get_div()
38 struct tegra_clk_frac_div *divider = to_clk_frac_div(hw); in clk_frac_div_recalc_rate() local
43 reg = readl_relaxed(divider->reg); in clk_frac_div_recalc_rate()
45 if ((divider->flags & TEGRA_DIVIDER_UART) && in clk_frac_div_recalc_rate()
49 div = (reg >> divider->shift) & div_mask(divider); in clk_frac_div_recalc_rate()
51 mul = get_mul(divider); in clk_frac_div_recalc_rate()
64 struct tegra_clk_frac_div *divider = to_clk_frac_div(hw); in clk_frac_div_round_rate() local
71 div = get_div(divider, rate, output_rate); in clk_frac_div_round_rate()
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| D | clk.h | 95 * struct tegra_clk_frac_div - fractional divider clock
98 * @reg: register containing divider
100 * @shift: shift to the divider bit field
101 * @width: width of the divider bit field
106 * TEGRA_DIVIDER_ROUND_UP - This flags indicates to round up the divider value.
108 * flag indicates that this divider is for fixed rate PLL.
110 * fraction bit is set. This flags indicates to calculate divider for which
112 * TEGRA_DIVIDER_UART - UART module divider has additional enable bit which is
113 * set when divider value is not 0. This flags indicates that the divider
158 * @n: feedback divider
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| /linux-6.12.1/drivers/clk/baikal-t1/ |
| D | ccu-div.h | 17 * CCU Divider private clock IDs
25 * CCU Divider private flags
26 * @CCU_DIV_BASIC: Basic divider clock required by the kernel as early as
28 * @CCU_DIV_SKIP_ONE: Due to some reason divider can't be set to 1.
30 * @CCU_DIV_SKIP_ONE_TO_THREE: For some reason divider can't be within [1,3].
42 * enum ccu_div_type - CCU Divider types
43 * @CCU_DIV_VAR: Clocks gate with variable divider.
44 * @CCU_DIV_GATE: Clocks gate with fixed divider.
45 * @CCU_DIV_BUF: Clock gate with no divider.
46 * @CCU_DIV_FIXED: Ungateable clock with fixed divider.
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| D | ccu-div.c | 78 unsigned long divider) in ccu_div_var_update_clkdiv() argument
85 nd = ccu_div_lock_delay_ns(parent_rate, divider); in ccu_div_var_update_clkdiv()
135 pr_err("Divider '%s' lock timed out\n", clk_hw_get_name(hw)); in ccu_div_var_enable()
211 unsigned long divider; in ccu_div_var_recalc_rate() local
215 divider = ccu_div_get(div->mask, val); in ccu_div_var_recalc_rate()
217 return ccu_div_calc_freq(parent_rate, divider); in ccu_div_var_recalc_rate()
224 unsigned long divider; in ccu_div_var_calc_divider() local
226 divider = parent_rate / rate; in ccu_div_var_calc_divider()
227 return clamp_t(unsigned long, divider, CCU_DIV_CLKDIV_MIN, in ccu_div_var_calc_divider()
235 unsigned long divider; in ccu_div_var_round_rate() local
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| /linux-6.12.1/drivers/clk/qcom/ |
| D | clk-regmap-divider.c | 11 #include "clk-regmap-divider.h"
21 struct clk_regmap_div *divider = to_clk_regmap_div(hw); in div_round_ro_rate() local
22 struct clk_regmap *clkr = ÷r->clkr; in div_round_ro_rate()
25 regmap_read(clkr->regmap, divider->reg, &val); in div_round_ro_rate()
26 val >>= divider->shift; in div_round_ro_rate()
27 val &= BIT(divider->width) - 1; in div_round_ro_rate()
29 return divider_ro_round_rate(hw, rate, prate, NULL, divider->width, in div_round_ro_rate()
36 struct clk_regmap_div *divider = to_clk_regmap_div(hw); in div_round_rate() local
38 return divider_round_rate(hw, rate, prate, NULL, divider->width, in div_round_rate()
45 struct clk_regmap_div *divider = to_clk_regmap_div(hw); in div_set_rate() local
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| /linux-6.12.1/drivers/clk/mvebu/ |
| D | dove-divider.c | 3 * Marvell Dove PMU Core PLL divider driver
15 #include "dove-divider.h"
53 unsigned int divider; in dove_get_divider() local
59 divider = val & ~(~0 << dc->div_bit_size); in dove_get_divider()
62 divider = dc->divider_table[divider]; in dove_get_divider()
64 return divider; in dove_get_divider()
70 unsigned int divider, max; in dove_calc_divider() local
72 divider = DIV_ROUND_CLOSEST(parent_rate, rate); in dove_calc_divider()
78 if (divider == dc->divider_table[i]) { in dove_calc_divider()
79 divider = i; in dove_calc_divider()
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| /linux-6.12.1/drivers/clk/xilinx/ |
| D | clk-xlnx-clock-wizard.c | 85 /* Divider limits, from UG572 Table 3-4 for Ultrascale+ */
111 /* Extract divider instance from clock hardware instance */
147 * struct clk_wzrd_divider - clock divider specific to clk_wzrd
150 * @base: base address of register containing the divider
151 * @offset: offset address of register containing the divider
152 * @shift: shift to the divider bit field
153 * @width: width of the divider bit field
154 * @flags: clk_wzrd divider flags
155 * @table: array of value/divider pairs, last entry should have div = 0
157 * @d: value of the common divider
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| /linux-6.12.1/drivers/clk/ |
| D | clk-divider.c | 7 * Adjustable divider clock implementation
20 * DOC: basic adjustable divider clock that cannot gate
29 static inline u32 clk_div_readl(struct clk_divider *divider) in clk_div_readl() argument
31 if (divider->flags & CLK_DIVIDER_BIG_ENDIAN) in clk_div_readl()
32 return ioread32be(divider->reg); in clk_div_readl()
34 return readl(divider->reg); in clk_div_readl()
37 static inline void clk_div_writel(struct clk_divider *divider, u32 val) in clk_div_writel() argument
39 if (divider->flags & CLK_DIVIDER_BIG_ENDIAN) in clk_div_writel()
40 iowrite32be(val, divider->reg); in clk_div_writel()
42 writel(val, divider->reg); in clk_div_writel()
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| D | clk-milbeaut.c | 379 struct m10v_clk_divider *divider = to_m10v_div(hw); in m10v_clk_divider_recalc_rate() local
382 val = readl(divider->reg) >> divider->shift; in m10v_clk_divider_recalc_rate()
383 val &= clk_div_mask(divider->width); in m10v_clk_divider_recalc_rate()
385 return divider_recalc_rate(hw, parent_rate, val, divider->table, in m10v_clk_divider_recalc_rate()
386 divider->flags, divider->width); in m10v_clk_divider_recalc_rate()
392 struct m10v_clk_divider *divider = to_m10v_div(hw); in m10v_clk_divider_round_rate() local
395 if (divider->flags & CLK_DIVIDER_READ_ONLY) { in m10v_clk_divider_round_rate()
398 val = readl(divider->reg) >> divider->shift; in m10v_clk_divider_round_rate()
399 val &= clk_div_mask(divider->width); in m10v_clk_divider_round_rate()
401 return divider_ro_round_rate(hw, rate, prate, divider->table, in m10v_clk_divider_round_rate()
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| /linux-6.12.1/drivers/clk/zynqmp/ |
| D | divider.c | 3 * Zynq UltraScale+ MPSoC Divider support
7 * Adjustable divider clock implementation
16 * DOC: basic adjustable divider clock that cannot gate
32 * struct zynqmp_clk_divider - adjustable divider clock
35 * @is_frac: The divider is a fractional divider
73 * zynqmp_clk_divider_recalc_rate() - Recalc rate of divider clock
82 struct zynqmp_clk_divider *divider = to_zynqmp_clk_divider(hw); in zynqmp_clk_divider_recalc_rate() local
84 u32 clk_id = divider->clk_id; in zynqmp_clk_divider_recalc_rate()
85 u32 div_type = divider->div_type; in zynqmp_clk_divider_recalc_rate()
92 pr_debug("%s() get divider failed for %s, ret = %d\n", in zynqmp_clk_divider_recalc_rate()
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| /linux-6.12.1/include/dt-bindings/clock/ |
| D | tegra234-clock.h | 36 /** @brief output of divider CLK_RST_CONTROLLER_CLK_M_DIVIDE */
52 * divided by the divider controlled by ACLK_CLK_DIVISOR in
56 /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_MSS_ENCRYPT switch divider output */
60 /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB switch divider output */
62 /** @brief CLK_RST_CONTROLLER_AON_NIC_RATE divider output */
64 /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC switch divider output */
81 /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_EQOS_AXI_CLK_0 divider gated output */
83 /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_EQOS_PTP_REF_CLK_0 divider gated output */
87 /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_EQOS_TX_CLK divider gated output */
152 /** @brief CLK_RST_CONTROLLER_MAUDCLK_OUT_SWITCH_DIVIDER switch divider output (maudclk) */
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| /linux-6.12.1/drivers/clk/imx/ |
| D | clk-fixup-div.c | 15 * struct clk_fixup_div - imx integer fixup divider clock
16 * @divider: the parent class
20 * The imx fixup divider clock is a subclass of basic clk_divider
24 struct clk_divider divider; member
31 struct clk_divider *divider = to_clk_divider(hw); in to_clk_fixup_div() local
33 return container_of(divider, struct clk_fixup_div, divider); in to_clk_fixup_div()
41 return fixup_div->ops->recalc_rate(&fixup_div->divider.hw, parent_rate); in clk_fixup_div_recalc_rate()
49 return fixup_div->ops->round_rate(&fixup_div->divider.hw, rate, prate); in clk_fixup_div_round_rate()
57 unsigned int divider, value; in clk_fixup_div_set_rate() local
61 divider = parent_rate / rate; in clk_fixup_div_set_rate()
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| D | clk-composite-8m.c | 31 struct clk_divider *divider = to_clk_divider(hw); in imx8m_clk_composite_divider_recalc_rate() local
36 prediv_value = readl(divider->reg) >> divider->shift; in imx8m_clk_composite_divider_recalc_rate()
37 prediv_value &= clk_div_mask(divider->width); in imx8m_clk_composite_divider_recalc_rate()
40 NULL, divider->flags, in imx8m_clk_composite_divider_recalc_rate()
41 divider->width); in imx8m_clk_composite_divider_recalc_rate()
43 div_value = readl(divider->reg) >> PCG_DIV_SHIFT; in imx8m_clk_composite_divider_recalc_rate()
47 divider->flags, PCG_DIV_WIDTH); in imx8m_clk_composite_divider_recalc_rate()
95 struct clk_divider *divider = to_clk_divider(hw); in imx8m_clk_composite_divider_set_rate() local
107 spin_lock_irqsave(divider->lock, flags); in imx8m_clk_composite_divider_set_rate()
109 orig = readl(divider->reg); in imx8m_clk_composite_divider_set_rate()
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| /linux-6.12.1/drivers/clk/rockchip/ |
| D | clk-half-divider.c | 25 struct clk_divider *divider = to_clk_divider(hw); in clk_half_divider_recalc_rate() local
28 val = readl(divider->reg) >> divider->shift; in clk_half_divider_recalc_rate()
29 val &= div_mask(divider->width); in clk_half_divider_recalc_rate()
60 * The maximum divider we can use without overflowing in clk_half_divider_bestdiv()
70 * parent rate, so return the divider immediately. in clk_half_divider_bestdiv()
98 struct clk_divider *divider = to_clk_divider(hw); in clk_half_divider_round_rate() local
102 divider->width, in clk_half_divider_round_rate()
103 divider->flags); in clk_half_divider_round_rate()
111 struct clk_divider *divider = to_clk_divider(hw); in clk_half_divider_set_rate() local
118 value = min_t(unsigned int, value, div_mask(divider->width)); in clk_half_divider_set_rate()
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| /linux-6.12.1/drivers/clk/mxs/ |
| D | clk-div.c | 12 * struct clk_div - mxs integer divider clock
13 * @divider: the parent class
18 * The mxs divider clock is a subclass of basic clk_divider with an
22 struct clk_divider divider; member
30 struct clk_divider *divider = to_clk_divider(hw); in to_clk_div() local
32 return container_of(divider, struct clk_div, divider); in to_clk_div()
40 return div->ops->recalc_rate(&div->divider.hw, parent_rate); in clk_div_recalc_rate()
48 return div->ops->round_rate(&div->divider.hw, rate, prate); in clk_div_round_rate()
57 ret = div->ops->set_rate(&div->divider.hw, rate, parent_rate); in clk_div_set_rate()
90 div->divider.reg = reg; in mxs_clk_div()
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| /linux-6.12.1/drivers/clk/stm32/ |
| D | clk-stm32-core.c | 212 const struct stm32_div_cfg *divider = &data->dividers[div_id]; in stm32_divider_get_rate() local
216 val = readl(base + divider->offset) >> divider->shift; in stm32_divider_get_rate()
217 val &= clk_div_mask(divider->width); in stm32_divider_get_rate()
218 div = _get_div(divider->table, val, divider->flags, divider->width); in stm32_divider_get_rate()
221 WARN(!(divider->flags & CLK_DIVIDER_ALLOW_ZERO), in stm32_divider_get_rate()
235 const struct stm32_div_cfg *divider = &data->dividers[div_id]; in stm32_divider_set_rate() local
239 value = divider_get_val(rate, parent_rate, divider->table, in stm32_divider_set_rate()
240 divider->width, divider->flags); in stm32_divider_set_rate()
244 if (divider->flags & CLK_DIVIDER_HIWORD_MASK) { in stm32_divider_set_rate()
245 val = clk_div_mask(divider->width) << (divider->shift + 16); in stm32_divider_set_rate()
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| /linux-6.12.1/drivers/media/tuners/ |
| D | tda18218_priv.h | 20 #define R07_MD1 0x07 /* Main divider byte 1 */
22 #define R09_MD2 0x09 /* Main divider byte 2 */
23 #define R0A_MD3 0x0a /* Main divider byte 1 */
24 #define R0B_MD4 0x0b /* Main divider byte 4 */
25 #define R0C_MD5 0x0c /* Main divider byte 5 */
26 #define R0D_MD6 0x0d /* Main divider byte 6 */
27 #define R0E_MD7 0x0e /* Main divider byte 7 */
28 #define R0F_MD8 0x0f /* Main divider byte 8 */
29 #define R10_CD1 0x10 /* Call divider byte 1 */
30 #define R11_CD2 0x11 /* Call divider byte 2 */
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| /linux-6.12.1/Documentation/devicetree/bindings/iio/afe/ |
| D | voltage-divider.yaml | 4 $id: http://devicetree.org/schemas/iio/afe/voltage-divider.yaml#
7 title: Voltage divider
13 When an io-channel measures the midpoint of a voltage divider, the
15 of the divider. This binding describes the voltage divider in such
35 const: voltage-divider
45 output channel, the voltage divider can act as a provider of
48 such as a voltage divider, and then consuming its raw value
49 isn't interesting. In this case, the voltage before the divider
59 Resistance R + Rout for the full divider. The io-channel is scaled by
75 * voltage divider (R = 200 Ohms, Rout = 22 Ohms) and fed to an ADC.
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| /linux-6.12.1/Documentation/devicetree/bindings/clock/ti/ |
| D | divider.txt | 1 Binding for TI divider clock
4 register-mapped adjustable clock rate divider that does not gate and has
42 The binding must also provide the register to control the divider and
43 unless the divider array is provided, min and max dividers. Optionally
54 - compatible : shall be "ti,divider-clock" or "ti,composite-divider-clock".
57 - reg : offset for register controlling adjustable divider
62 - ti,bit-shift : number of bits to shift the divider value, defaults to 0
76 - ti,latch-bit : latch the divider value to HW, only needed if the register
77 access requires this. As an example dra76x DPLL_GMAC H14 divider implements
83 compatible = "ti,divider-clock";
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| /linux-6.12.1/Documentation/devicetree/bindings/clock/ |
| D | xgene.txt | 37 reset and/or the divider. Either may be omitted, but at least
55 - divider-offset : Offset to the divider CSR register from the divider base.
57 - divider-width : Width of the divider register. Default is 0.
58 - divider-shift : Bit shift of the divider register. Default is 0.
107 divider-offset = <0x238>;
108 divider-width = <0x9>;
109 divider-shift = <0x0>;
125 divider-offset = <0x10>;
126 divider-width = <0x2>;
127 divider-shift = <0x0>;
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| /linux-6.12.1/drivers/gpu/drm/amd/amdgpu/ |
| D | amdgpu_pll.c | 70 * amdgpu_pll_get_fb_ref_div - feedback and ref divider calculation
75 * @post_div: post divider
76 * @fb_div_max: feedback divider maximum
77 * @ref_div_max: reference divider maximum
78 * @fb_div: resulting feedback divider
79 * @ref_div: resulting reference divider
81 * Calculate feedback and reference divider for a given post divider. Makes
90 /* limit reference * post divider to a maximum */ in amdgpu_pll_get_fb_ref_div()
96 /* get matching reference and feedback divider */ in amdgpu_pll_get_fb_ref_div()
100 /* limit fb divider to its maximum */ in amdgpu_pll_get_fb_ref_div()
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| /linux-6.12.1/drivers/clk/sophgo/ |
| D | clk-sg2042-clkgen.c | 72 * struct sg2042_divider_clock - Divider clock
79 * @offset_ctrl: offset of divider control registers
80 * @shift: shift of "Clock Divider Factor" in divider control register
81 * @width: width of "Clock Divider Factor" in divider control register
83 * @initval: In the divider control register, we can configure whether
84 * to use the value of "Clock Divider Factor" or just use
89 * value when poweron) and default value of "Clock Divider
160 struct sg2042_divider_clock *divider = to_sg2042_clk_divider(hw); in sg2042_clk_divider_recalc_rate() local
164 if (!(readl(divider->reg) & BIT(SHIFT_DIV_FACTOR_SEL))) { in sg2042_clk_divider_recalc_rate()
165 val = divider->initval; in sg2042_clk_divider_recalc_rate()
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| /linux-6.12.1/drivers/clk/bcm/ |
| D | clk-kona.h | 220 * output rate of the clock. Each divider can be either fixed or
221 * variable. If there are two dividers, they are the "pre-divider"
222 * and the "regular" or "downstream" divider. If there is only one,
223 * there is no pre-divider.
225 * A fixed divider is any non-zero (positive) value, and it
226 * indicates how the input rate is affected by the divider.
228 * The value of a variable divider is maintained in a sub-field of a
229 * 32-bit divider register. The position of the field in the
233 * In addition, a variable divider can indicate that some subset
234 * of its bits represent a "fractional" part of the divider. Such
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| /linux-6.12.1/drivers/clk/ingenic/ |
| D | cgu.h | 27 * @n_shift: the number of bits to shift the divider value by (ie. the
28 * index of the lowest bit of the divider value in the PLL's
30 * @n_bits: the size of the divider field in bits
31 * @n_offset: the divider value which encodes to 0 in the PLL's control
33 * @od_shift: the number of bits to shift the post-VCO divider value by (ie.
34 * the index of the lowest bit of the post-VCO divider value in
36 * @od_bits: the size of the post-VCO divider field in bits, or 0 if no
38 * @od_max: the maximum post-VCO divider value
39 * @od_encoding: a pointer to an array mapping post-VCO divider values to
84 * struct ingenic_cgu_div_info - information about a divider
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