Lines Matching full:divider
3 * Zynq UltraScale+ MPSoC Divider support
7 * Adjustable divider clock implementation
16 * DOC: basic adjustable divider clock that cannot gate
32 * struct zynqmp_clk_divider - adjustable divider clock
35 * @is_frac: The divider is a fractional divider
73 * zynqmp_clk_divider_recalc_rate() - Recalc rate of divider clock
82 struct zynqmp_clk_divider *divider = to_zynqmp_clk_divider(hw); in zynqmp_clk_divider_recalc_rate() local
84 u32 clk_id = divider->clk_id; in zynqmp_clk_divider_recalc_rate()
85 u32 div_type = divider->div_type; in zynqmp_clk_divider_recalc_rate()
92 pr_debug("%s() get divider failed for %s, ret = %d\n", in zynqmp_clk_divider_recalc_rate()
100 if (divider->flags & CLK_DIVIDER_POWER_OF_TWO) in zynqmp_clk_divider_recalc_rate()
104 WARN(!(divider->flags & CLK_DIVIDER_ALLOW_ZERO), in zynqmp_clk_divider_recalc_rate()
114 * zynqmp_clk_divider_round_rate() - Round rate of divider clock
125 struct zynqmp_clk_divider *divider = to_zynqmp_clk_divider(hw); in zynqmp_clk_divider_round_rate() local
127 u32 clk_id = divider->clk_id; in zynqmp_clk_divider_round_rate()
128 u32 div_type = divider->div_type; in zynqmp_clk_divider_round_rate()
134 if (divider->flags & CLK_DIVIDER_READ_ONLY) { in zynqmp_clk_divider_round_rate()
138 pr_debug("%s() get divider failed for %s, ret = %d\n", in zynqmp_clk_divider_round_rate()
145 if (divider->flags & CLK_DIVIDER_POWER_OF_TWO) in zynqmp_clk_divider_round_rate()
151 width = fls(divider->max_div); in zynqmp_clk_divider_round_rate()
153 rate = divider_round_rate(hw, rate, prate, NULL, width, divider->flags); in zynqmp_clk_divider_round_rate()
155 if (divider->is_frac && (clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT) && (rate % *prate)) in zynqmp_clk_divider_round_rate()
162 * zynqmp_clk_divider_set_rate() - Set rate of divider clock
172 struct zynqmp_clk_divider *divider = to_zynqmp_clk_divider(hw); in zynqmp_clk_divider_set_rate() local
174 u32 clk_id = divider->clk_id; in zynqmp_clk_divider_set_rate()
175 u32 div_type = divider->div_type; in zynqmp_clk_divider_set_rate()
179 value = zynqmp_divider_get_val(parent_rate, rate, divider->flags); in zynqmp_clk_divider_set_rate()
188 if (divider->flags & CLK_DIVIDER_POWER_OF_TWO) in zynqmp_clk_divider_set_rate()
194 pr_debug("%s() set divider failed for %s, ret = %d\n", in zynqmp_clk_divider_set_rate()
214 * @type: Divider type
263 * zynqmp_clk_register_divider() - Register a divider clock
270 * Return: clock hardware to registered clock divider
283 /* allocate the divider */ in zynqmp_clk_register_divider()
308 * To achieve best possible rate, maximum limit of divider is required in zynqmp_clk_register_divider()