clk/bcm/clk-kona.h

220  * output rate of the clock.  Each divider can be either fixed or
221  * variable.  If there are two dividers, they are the "pre-divider"
222  * and the "regular" or "downstream" divider.  If there is only one,
223  * there is no pre-divider.
225  * A fixed divider is any non-zero (positive) value, and it
226  * indicates how the input rate is affected by the divider.
228  * The value of a variable divider is maintained in a sub-field of a
229  * 32-bit divider register.  The position of the field in the
233  * In addition, a variable divider can indicate that some subset
234  * of its bits represent a "fractional" part of the divider.  Such
235  * bits comprise the low-order portion of the divider field, and can
236  * be viewed as representing the portion of the divider that lies to
242  * code a divider field value is distinguished from the value it
245  * In order to avoid dealing with fractions, divider arithmetic is
247  * been left-shifted by the fractional width of a divider.  Dividing
252  * The recorded value of a variable divider can be modified.  To
253  * modify either divider (or both), a clock must be enabled (i.e.,
260 		struct {	/* variable divider */
261 			u32 offset;	/* divider register offset */
266 			u64 scaled_div;	/* scaled divider value */
268 		u32 fixed;	/* non-zero fixed divider value */
274  * Divider flags:
275  *   EXISTS means this divider exists
276  *   FIXED means it is a fixed-rate divider
278 #define BCM_CLK_DIV_FLAGS_EXISTS	((u32)1 << 0)	/* Divider is valid */
281 /* Divider initialization macros */
283 /* A fixed (non-zero) divider */
290 /* A divider with an integral divisor */
291 #define DIVIDER(_offset, _shift, _width)				\  macro
300 /* A divider whose divisor has an integer and fractional part */
351  * Making changes to a variable divider or a selector for a clock
360  * selector and/or its pre-divider.