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/linux-6.12.1/Documentation/devicetree/bindings/clock/
Dfixed-clock.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/clock/fixed-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Simple fixed-rate clock sources
10 - Michael Turquette <mturquette@baylibre.com>
11 - Stephen Boyd <sboyd@kernel.org>
16 - description:
17 Preferred name is 'clock-<freq>' with <freq> being the output
18 frequency as defined in the 'clock-frequency' property.
[all …]
/linux-6.12.1/drivers/clk/
Dclk-fixed-rate.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2010-2011 Canonical Ltd <jeremy.kerr@canonical.com>
4 * Copyright (C) 2011-2012 Mike Turquette, Linaro Ltd <mturquette@linaro.org>
6 * Fixed rate clock implementation
9 #include <linux/clk-provider.h>
18 * DOC: basic fixed-rate clock that cannot gate
20 * Traits of this clock:
21 * prepare - clk_(un)prepare only ensures parents are prepared
22 * enable - clk_enable only ensures parents are enabled
23 * rate - rate is always a fixed value. No clk_set_rate support
[all …]
Dkunit_clk_fixed_rate_test.dtso1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
5 #include "clk-fixed-rate_test.h"
8 fixed_50MHz: kunit-clock {
9 compatible = "fixed-clock";
10 #clock-cells = <0>;
11 clock-frequency = <TEST_FIXED_FREQUENCY>;
12 clock-accuracy = <TEST_FIXED_ACCURACY>;
15 kunit-clock-consumer {
16 compatible = "test,single-clk-consumer";
Dclk.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2010-2011 Canonical Ltd <jeremy.kerr@canonical.com>
4 * Copyright (C) 2011-2012 Linaro Ltd <mturquette@linaro.org>
6 * Standard functionality for the common clock API. See Documentation/driver-api/clk.rst
10 #include <linux/clk-provider.h>
11 #include <linux/clk/clk-conf.h>
85 unsigned long accuracy; member
116 if (!core->rpm_enabled) in clk_pm_runtime_get()
119 return pm_runtime_resume_and_get(core->dev); in clk_pm_runtime_get()
124 if (!core->rpm_enabled) in clk_pm_runtime_put()
[all …]
/linux-6.12.1/Documentation/timers/
Dtimekeeping.rst2 Clock sources, Clock events, sched_clock() and delay timers
10 If you grep through the kernel source you will find a number of architecture-
11 specific implementations of clock sources, clockevents and several likewise
12 architecture-specific overrides of the sched_clock() function and some
15 To provide timekeeping for your platform, the clock source provides
16 the basic timeline, whereas clock events shoot interrupts on certain points
17 on this timeline, providing facilities such as high-resolution timers.
22 Clock sources
23 -------------
25 The purpose of the clock source is to provide a timeline for the system that
[all …]
/linux-6.12.1/Documentation/hwmon/
Dpc87360.rst22 -----------------
27 - 0: None
28 - **1**: Forcibly enable internal voltage and temperature channels,
30 - 2: Forcibly enable all voltage and temperature channels, except in9
31 - 3: Forcibly enable all voltage and temperature channels, including in9
42 -----------
56 PC87360 - 2 2 - 0xE1
57 PC87363 - 2 2 - 0xE8
58 PC87364 - 3 3 - 0xE4
60 PC87366 11 3 3 3-4 0xE9
[all …]
Dshtc1.rst41 -----------
48 address 0x70. See Documentation/i2c/instantiating-devices.rst for methods to
53 1. blocking (pull the I2C clock line down while performing the measurement) or
54 non-blocking mode. Blocking mode will guarantee the fastest result but
55 the I2C bus will be busy during that time. By default, non-blocking mode
56 is used. Make sure clock-stretching works properly on your device if you
58 2. high or low accuracy. High accuracy is used by default and using it is
61 sysfs-Interface
62 ---------------
65 - temperature input
[all …]
/linux-6.12.1/include/linux/
Dclk-provider.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright (c) 2010-2011 Jeremy Kerr <jeremy.kerr@canonical.com>
4 * Copyright (C) 2011-2012 Linaro Ltd <mturquette@linaro.org>
14 * top-level framework. custom flags for dealing with hardware specifics
20 #define CLK_SET_PARENT_GATE BIT(1) /* must be gated across re-parent */
26 #define CLK_SET_RATE_NO_REPARENT BIT(7) /* don't re-parent on rate change */
27 #define CLK_GET_ACCURACY_NOCACHE BIT(8) /* do not use the cached clk accuracy */
29 #define CLK_SET_RATE_UNGATE BIT(10) /* clock needs to run to set rate */
31 /* parents need enable during gate/ungate, set rate and re-parent */
33 /* duty cycle call may be forwarded to the parent clock */
[all …]
Dhrtimer_defs.h1 /* SPDX-License-Identifier: GPL-2.0 */
14 * idea of the (in)accuracy of timers. Timer values are rounded up to
36 * struct hrtimer_clock_base - the timer base for a specific clock
37 * @cpu_base: per cpu clock base
38 * @index: clock type index for per_cpu support when moving a
40 * @clockid: clock id for per_cpu support
44 * @get_time: function to retrieve the current time of the clock
45 * @offset: offset of this clock to the monotonic base
71 * struct hrtimer_cpu_base - the per cpu clock bases
72 * @lock: lock protecting the base and associated clock bases
[all …]
/linux-6.12.1/arch/arm/boot/dts/alphascale/
Dalphascale-asm9260.dtsi2 * Copyright 2014 Oleksij Rempel <linux@rempel-privat.de>
7 #include <dt-bindings/clock/alphascale,asm9260.h>
10 #address-cells = <1>;
11 #size-cells = <1>;
12 interrupt-parent = <&icoll>;
20 #address-cells = <0>;
21 #size-cells = <0>;
24 compatible = "arm,arm926ej-s";
31 compatible = "fixed-clock";
32 #clock-cells = <0>;
[all …]
/linux-6.12.1/Documentation/sound/designs/
Dtimestamping.rst7 - Trigger_tstamp is the system time snapshot taken when the .trigger
11 estimate with a delay. In the latter two cases, the low-level driver
17 - tstamp is the current system timestamp updated during the last
19 The difference (tstamp - trigger_tstamp) defines the elapsed time.
29 - ``avail`` reports how much can be written in the ring buffer
30 - ``delay`` reports the time it will take to hear a new sample after all
43 ascii-art, this could be represented as follows (for the playback
47 --------------------------------------------------------------> time
53 |< codec delay >|<--hw delay-->|<queued samples>|<---avail->|
54 |<----------------- delay---------------------->| |
[all …]
/linux-6.12.1/arch/arm/boot/dts/intel/pxa/
Dpxa300-raumfeld-tuneable-clock.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 #include <dt-bindings/clock/maxim,max9485.h>
6 xo_27mhz: oscillator-27mhz {
7 compatible = "fixed-clock";
8 #clock-cells = <0>;
9 clock-frequency = <27000000>;
10 clock-accuracy = <100>;
14 compatible = "simple-audio-card";
15 simple-audio-card,name = "Raumfeld Speaker";
16 #address-cells = <1>;
[all …]
Dpxa300-raumfeld-speaker-one.dts1 // SPDX-License-Identifier: GPL-2.0
3 /dts-v1/;
5 #include "pxa300-raumfeld-common.dtsi"
9 compatible = "raumfeld,raumfeld-speaker-one-pxa303", "marvell,pxa300";
13 #sound-dai-cells = <0>;
14 Vdd-supply = <&reg_3v3>;
15 Vdda-supply = <&reg_va_5v0>;
18 xo_11mhz: oscillator-11mhz {
19 compatible = "fixed-clock";
20 #clock-cells = <0>;
[all …]
/linux-6.12.1/arch/x86/kernel/
Dtsc_msr.c1 // SPDX-License-Identifier: GPL-2.0
14 #include <asm/intel-family.h>
23 * lot of accuracy which leads to clock drift. As far as we know Bay Trail SoCs
26 * unclear if the root PLL outputs are used directly by the CPU clock PLL or
30 * So we can create a simplified model of the CPU clock setup using a reference
31 * clock of 100 MHz plus a quotient which gets us as close to the frequency
62 * Penwell and Clovertrail use spread spectrum clock,
161 * MSR-based CPU/TSC frequency discovery for certain CPUs.
179 freq_desc = (struct freq_desc *)id->driver_data; in cpu_khz_from_msr()
180 if (freq_desc->use_msr_plat) { in cpu_khz_from_msr()
[all …]
Dpvclock.c1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /* paravirtual clock -- common code used by kvm/xen
31 do_div(pv_tsc_khz, src->tsc_to_system_mul); in pvclock_tsc_khz()
32 if (src->tsc_shift < 0) in pvclock_tsc_khz()
33 pv_tsc_khz <<= -src->tsc_shift; in pvclock_tsc_khz()
35 pv_tsc_khz >>= src->tsc_shift; in pvclock_tsc_khz()
61 flags = src->flags; in pvclock_read_flags()
78 flags = src->flags; in __pvclock_clocksource_read()
82 src->flags &= ~PVCLOCK_GUEST_STOPPED; in __pvclock_clocksource_read()
94 * does not sacrifice accuracy. in __pvclock_clocksource_read()
[all …]
/linux-6.12.1/drivers/clk/at91/
Ddt-compat.c1 // SPDX-License-Identifier: GPL-2.0
2 #include <linux/clk-provider.h>
33 const char *name = np->name; in of_sama5d2_clk_audio_pll_frac_setup()
53 "atmel,sama5d2-clk-audio-pll-frac",
59 const char *name = np->name; in of_sama5d2_clk_audio_pll_pad_setup()
79 "atmel,sama5d2-clk-audio-pll-pad",
85 const char *name = np->name; in of_sama5d2_clk_audio_pll_pmc_setup()
105 "atmel,sama5d2-clk-audio-pll-pmc",
161 if (of_property_read_string(np, "clock-output-names", &name)) in of_sama5d2_clk_generated_setup()
162 name = gcknp->name; in of_sama5d2_clk_generated_setup()
[all …]
/linux-6.12.1/drivers/video/fbdev/kyro/
DSTG4000InitDevice.c41 /* Core clock freq */
44 /* Reference Clock freq */
61 /* PLL Clock */
101 /* Program SD-RAM interface */ in InitSDRAMRegisters()
129 /* Translate clock in Hz */ in ProgramClock()
133 /* Work out acceptable clock in ProgramClock()
134 * The method calculates ~ +- 0.4% (1/256) in ProgramClock()
136 ulMinClock = coreClock - (coreClock >> 8); in ProgramClock()
139 /* Scale clock required for use in calculations */ in ProgramClock()
147 /* loop for pre-divider from min to max */ in ProgramClock()
[all …]
/linux-6.12.1/Documentation/devicetree/bindings/iio/adc/
Drenesas,rzg2l-adc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/iio/adc/renesas,rzg2l-adc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
13 A/D Converter block is a successive approximation analog-to-digital converter
14 with a 12-bit accuracy. Up to eight analog input channels can be selected.
16 stored in a 32-bit data register corresponding to each channel.
21 - enum:
22 - renesas,r9a07g043-adc # RZ/G2UL and RZ/Five
[all …]
Dti,adc12138.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Texas Instruments ADC12138 and similar self-calibrating ADCs
10 - Akinobu Mita <akinobu.mita@gmail.com>
19 - ti,adc12130
20 - ti,adc12132
21 - ti,adc12138
32 description: Conversion clock input.
34 vref-p-supply:
[all …]
/linux-6.12.1/tools/testing/selftests/kvm/x86_64/
Dhyperv_clock.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Tests for Hyper-V clocksources
59 /* For increased accuracy, take mean rdtsc() before and afrer rdmsr() */ in check_tsc_msr_rdtsc()
71 delta_ns = ((t2 - t1) * 100) - ((r2 - r1) * 1000000000 / tsc_freq); in check_tsc_msr_rdtsc()
73 delta_ns = -delta_ns; in check_tsc_msr_rdtsc()
76 GUEST_ASSERT(delta_ns * 100 < (t2 - t1) * 100); in check_tsc_msr_rdtsc()
81 return mul_u64_u64_shr64(rdtsc(), tsc_page->tsc_scale) + tsc_page->tsc_offset; in get_tscpage_ts()
93 GUEST_ASSERT(r1 >= t1 && r1 - t1 < 100000); in check_tsc_msr_tsc_page()
98 GUEST_ASSERT(r2 >= t1 && r2 - t2 < 100000); in check_tsc_msr_tsc_page()
105 /* Set Guest OS id to enable Hyper-V emulation */ in guest_main()
[all …]
/linux-6.12.1/Documentation/devicetree/bindings/mtd/
Dlpc32xx-mlc.txt4 - compatible: "nxp,lpc3220-mlc"
5 - reg: Address and size of the controller
6 - interrupts: The NAND interrupt specification
7 - gpios: GPIO specification for NAND write protect
11 Hz, to make them independent of actual clock speed and to provide for good
12 accuracy:)
13 - nxp,tcea_delay: TCEA_DELAY
14 - nxp,busy_delay: BUSY_DELAY
15 - nxp,nand_ta: NAND_TA
16 - nxp,rd_high: RD_HIGH
[all …]
/linux-6.12.1/drivers/crypto/intel/qat/qat_common/
Dadf_clock.c1 // SPDX-License-Identifier: GPL-2.0-only
58 delta_us = timespec_to_us(&ts2) - timespec_to_us(&ts1); in measure_clock()
59 } while (delta_us > MEASURE_CLOCK_DELTA_THRESHOLD_US && --tries); in measure_clock()
62 dev_err(&GET_DEV(accel_dev), "Excessive clock measure delay\n"); in measure_clock()
63 return -ETIMEDOUT; in measure_clock()
74 return -EIO; in measure_clock()
77 delta_us = timespec_to_us(&ts4) - timespec_to_us(&ts3); in measure_clock()
78 } while (delta_us > MEASURE_CLOCK_DELTA_THRESHOLD_US && --tries); in measure_clock()
81 dev_err(&GET_DEV(accel_dev), "Excessive clock measure delay\n"); in measure_clock()
82 return -ETIMEDOUT; in measure_clock()
[all …]
/linux-6.12.1/Documentation/devicetree/bindings/iio/pressure/
Dhoneywell,hsc030pa.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
23 pressure-triplet (directly extracted from the part number) or in case it's
27 by the sensor. pmin-pascal and pmax-pascal corespond to the minimum and
30 Please note that in case of an SPI-based sensor, the clock signal should not
34 …-edam.honeywell.com/content/dam/honeywell-edam/sps/siot/en-us/products/sensors/pressure-sensors/bo…
35 …-edam.honeywell.com/content/dam/honeywell-edam/sps/siot/en-us/products/sensors/pressure-sensors/bo…
38 - Petre Rodan <petre.rodan@subdimension.ro>
47 honeywell,transfer-function:
[all …]
/linux-6.12.1/drivers/staging/media/atomisp/pci/
Datomisp_csi2.c1 // SPDX-License-Identifier: GPL-2.0
19 #include <media/v4l2-event.h>
20 #include <media/v4l2-mediabus.h>
23 #include "atomisp-regs.h"
34 return &csi2->formats[pad]; in __csi2_get_format()
38 * csi2_enum_mbus_code - Handle pixel format enumeration
42 * return -EINVAL or zero on success
51 while (ic->code) { in csi2_enum_mbus_code()
52 if (i == code->index) { in csi2_enum_mbus_code()
53 code->code = ic->code; in csi2_enum_mbus_code()
[all …]
/linux-6.12.1/kernel/time/
Djiffies.c1 // SPDX-License-Identifier: GPL-2.0+
13 #include "tick-internal.h"
23 * denominator clock source which should function on
30 * for "tick-less" systems.
86 refined_jiffies.name = "refined-jiffies"; in register_refined_jiffies()
91 /* shift_hz stores hz<<8 for extra accuracy */ in register_refined_jiffies()

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