Lines Matching +full:clock +full:- +full:accuracy

41 /* Core clock freq */
44 /* Reference Clock freq */
61 /* PLL Clock */
101 	/* Program SD-RAM interface */  in InitSDRAMRegisters()
129 	/* Translate clock in Hz */  in ProgramClock()
133 	/* Work out acceptable clock  in ProgramClock()
134 	 * The method calculates ~ +- 0.4% (1/256)  in ProgramClock()
136 	ulMinClock = coreClock - (coreClock >> 8);  in ProgramClock()
139 	/* Scale clock required for use in calculations */  in ProgramClock()
147 		/* loop for pre-divider from min to max  */  in ProgramClock()
155 			/* compensate for accuracy */  in ProgramClock()
157 				F--;  in ProgramClock()
167 				/* Calc VCO at full accuracy */  in ProgramClock()
181 					ulTmp = (ulVCO >> OD);	/* Clock = VCO / (2^OD) */  in ProgramClock()
183 					/* Is this clock good enough? */  in ProgramClock()
186 …ulPhaseScore = (((refClock / R) - (refClock / STG4K3_PLL_MAX_R))) / ((refClock - (refClock / STG4K…  in ProgramClock()
188 …ulVcoScore = ((ulVCO - STG4K3_PLL_MINR_VCO)) / ((STG4K3_PLL_MAXR_VCO - STG4K3_PLL_MINR_VCO) >> 10);  in ProgramClock()
200 			/*--------------------------------------------------------------------------  in ProgramClock()
206 …                       --------------------------------------------------------------------------*/  in ProgramClock()
277 		                         (u32)pDev->revision);  in SetCoreClockPLL()
280 		return -EINVAL;  in SetCoreClockPLL()
284 	core_pll |= ((P) | ((F - 2) << 2) | ((R - 2) << 11));  in SetCoreClockPLL()
291 	/* Without some delay between the PCI config writes the clock does  in SetCoreClockPLL()
292 	   not reliably set when the code is compiled -O3  in SetCoreClockPLL()