Lines Matching +full:clock +full:- +full:accuracy
1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright (c) 2010-2011 Jeremy Kerr <jeremy.kerr@canonical.com>
4 * Copyright (C) 2011-2012 Linaro Ltd <mturquette@linaro.org>
14 * top-level framework. custom flags for dealing with hardware specifics
20 #define CLK_SET_PARENT_GATE BIT(1) /* must be gated across re-parent */
26 #define CLK_SET_RATE_NO_REPARENT BIT(7) /* don't re-parent on rate change */
27 #define CLK_GET_ACCURACY_NOCACHE BIT(8) /* do not use the cached clk accuracy */
29 #define CLK_SET_RATE_UNGATE BIT(10) /* clock needs to run to set rate */
31 /* parents need enable during gate/ungate, set rate and re-parent */
33 /* duty cycle call may be forwarded to the parent clock */
42 * struct clk_rate_request - Structure encoding the clk constraints that
43 * a clock user might require.
48 * @rate: Requested clock rate. This field will be adjusted by
49 * clock drivers according to hardware capabilities.
54 * @best_parent_hw: The most appropriate parent clock that fulfills the
77 * struct clk_duty - Structure encoding the duty cycle ratio of a clock
88 * struct clk_ops - Callback operations for hardware clocks; these are to
89 * be provided by the clock implementation, and will be called by drivers
92 * @prepare: Prepare the clock for enabling. This must not return until
93 * the clock is fully prepared, and it's safe to call clk_enable.
94 * This callback is intended to allow clock implementations to
98 * @unprepare: Release the clock from its prepared state. This will typically
102 * @is_prepared: Queries the hardware to determine if the clock is prepared.
106 * @unprepare_unused: Unprepare the clock atomically. Only called from
110 * @enable: Enable the clock atomically. This must not return until the
111 * clock is generating a valid clock signal, usable by consumer
115 * @disable: Disable the clock atomically. Called with enable_lock held.
118 * @is_enabled: Queries the hardware to determine if the clock is enabled.
122 * @disable_unused: Disable the clock atomically. Only called from
127 * @save_context: Save the context of the clock in prepration for poweroff.
129 * @restore_context: Restore the context of the clock after a restoration
132 * @recalc_rate: Recalculate the rate of this clock, by querying hardware. The
135 * driver cannot figure out a rate for this clock, it must return
136 * 0. Returns the calculated rate. Optional, but recommended - if
137 * this op is not set then clock rate will be initialized to 0.
140 * supported by the clock. The parent rate is an input/output
144 * actually supported by the clock, and optionally the parent clock
145 * that should be used to provide the clock rate.
147 * @set_parent: Change the input source of this clock; for clocks with multiple
152 * Returns 0 on success, -EERROR otherwise.
154 * @get_parent: Queries the hardware to determine the parent of a clock. The
156 * the parent clock. This index can be applied to either the
159 * index. Currently only called when the clock is initialized by
164 * @set_rate: Change the rate of this clock. The requested rate is specified
168 * Returns 0 on success, -EERROR otherwise.
170 * @set_rate_and_parent: Change the rate and the parent of this clock. The
179 * Returns 0 on success, -EERROR otherwise.
181 * @recalc_accuracy: Recalculate the accuracy of this clock. The clock accuracy
182 * is expressed in ppb (parts per billion). The parent accuracy is
184 * Returns the calculated accuracy. Optional - if this op is not
185 * set then clock accuracy will be initialized to parent accuracy
186 * or 0 (perfect clock) if clock has no parent.
188 * @get_phase: Queries the hardware to get the current phase of a clock.
189 * Returned values are 0-359 degrees on success, negative
192 * @set_phase: Shift the phase this clock signal in degrees specified
194 * 0-359. Return 0 on success, otherwise -EERROR.
197 * of a clock. Returned values denominator cannot be 0 and must be
200 * @set_duty_cycle: Apply the duty cycle ratio to this clock signal specified by
203 * and >= numerator) Return 0 on success, otherwise -EERROR.
205 * @init: Perform platform-specific initialization magic.
206 * This is not used by any of the basic clock types.
209 * clock. It may also be used dynamic resource allocation is
210 * required. It shall not used to deal with clock parameters,
212 * Returns 0 on success, -EERROR otherwise.
216 * @debug_init: Set up type-specific debugfs entries for this clock. This
218 * clock has been created. The dentry pointer representing that
220 * prepare_lock held. Returns 0 on success, -EERROR otherwise.
225 * (prepare) contexts. If enabling a clock requires code that might sleep,
226 * this must be done in clk_prepare. Clock enable code that will never be
229 * Typically, drivers will call clk_prepare when a clock may be needed later
230 * (eg. when a device is opened), and clk_enable when the clock is actually
272 * struct clk_parent_data - clk parent information
286 * struct clk_init_data - holds init data that's common to all clocks and is
287 * shared between the clock provider and the common clock framework.
289 * @name: clock name
290 * @ops: operations this clock supports
297 * @flags: framework-level hints and quirks
311 * struct clk_hw - handle for traversing from a struct clk to its corresponding
312 * hardware-specific structure. struct clk_hw should be declared within struct
319 * @clk: pointer to the per-user struct clk instance that can be used to call
323 * with the common clock framework. This pointer will be set to NULL once
333 * DOC: Basic clock implementations common to many platforms
335 * Each basic clock hardware type is comprised of a structure describing the
336 * clock hardware, implementations of the relevant callbacks in struct clk_ops,
342 * struct clk_fixed_rate - fixed-rate clock
343 * @hw: handle between common and hardware-specific interfaces
344 * @fixed_rate: constant frequency of clock
345 * @fixed_accuracy: constant accuracy of clock in ppb (parts per billion)
349 * * CLK_FIXED_RATE_PARENT_ACCURACY - Use the accuracy of the parent clk
372 * clk_hw_register_fixed_rate - register fixed-rate clock with the clock
374 * @dev: device that is registering this clock
375 * @name: name of this clock
376 * @parent_name: name of clock's parent
377 * @flags: framework-specific flags
378 * @fixed_rate: non-adjustable clock rate
385 * devm_clk_hw_register_fixed_rate - register fixed-rate clock with the clock
387 * @dev: device that is registering this clock
388 * @name: name of this clock
389 * @parent_name: name of clock's parent
390 * @flags: framework-specific flags
391 * @fixed_rate: non-adjustable clock rate
397 * devm_clk_hw_register_fixed_rate_parent_data - register fixed-rate clock with
398 * the clock framework
399 * @dev: device that is registering this clock
400 * @name: name of this clock
402 * @flags: framework-specific flags
403 * @fixed_rate: non-adjustable clock rate
411 * clk_hw_register_fixed_rate_parent_hw - register fixed-rate clock with
412 * the clock framework
413 * @dev: device that is registering this clock
414 * @name: name of this clock
416 * @flags: framework-specific flags
417 * @fixed_rate: non-adjustable clock rate
424 * clk_hw_register_fixed_rate_parent_data - register fixed-rate clock with
425 * the clock framework
426 * @dev: device that is registering this clock
427 * @name: name of this clock
429 * @flags: framework-specific flags
430 * @fixed_rate: non-adjustable clock rate
438 * clk_hw_register_fixed_rate_with_accuracy - register fixed-rate clock with
439 * the clock framework
440 * @dev: device that is registering this clock
441 * @name: name of this clock
442 * @parent_name: name of clock's parent
443 * @flags: framework-specific flags
444 * @fixed_rate: non-adjustable clock rate
445 * @fixed_accuracy: non-adjustable clock accuracy
454 * clk_hw_register_fixed_rate_with_accuracy_parent_hw - register fixed-rate
455 * clock with the clock framework
456 * @dev: device that is registering this clock
457 * @name: name of this clock
459 * @flags: framework-specific flags
460 * @fixed_rate: non-adjustable clock rate
461 * @fixed_accuracy: non-adjustable clock accuracy
469 * clk_hw_register_fixed_rate_with_accuracy_parent_data - register fixed-rate
470 * clock with the clock framework
471 * @dev: device that is registering this clock
472 * @name: name of this clock
473 * @parent_data: name of clock's parent
474 * @flags: framework-specific flags
475 * @fixed_rate: non-adjustable clock rate
476 * @fixed_accuracy: non-adjustable clock accuracy
484 * clk_hw_register_fixed_rate_parent_accuracy - register fixed-rate clock with
485 * the clock framework
486 * @dev: device that is registering this clock
487 * @name: name of this clock
488 * @parent_data: name of clock's parent
489 * @flags: framework-specific flags
490 * @fixed_rate: non-adjustable clock rate
504 * struct clk_gate - gating clock
506 * @hw: handle between common and hardware-specific interfaces
509 * @flags: hardware-specific flags
512 * Clock which can gate its output. Implements .enable & .disable
515 * CLK_GATE_SET_TO_DISABLE - by default this clock sets the bit at bit_idx to
516 * enable the clock. Setting this flag does the opposite: setting the bit
517 * disable the clock and clearing it enables the clock
518 * CLK_GATE_HIWORD_MASK - The gate settings are only in lower 16-bit
519 * of this register, and mask of gate bits are in higher 16-bit of this
520 * register. While setting the gate bits, higher 16-bit should also be
522 * CLK_GATE_BIG_ENDIAN - by default little endian register accesses are used for
560 * clk_hw_register_gate - register a gate clock with the clock framework
561 * @dev: device that is registering this clock
562 * @name: name of this clock
563 * @parent_name: name of this clock's parent
564 * @flags: framework-specific flags for this clock
565 * @reg: register address to control gating of this clock
566 * @bit_idx: which bit in the register controls gating of this clock
567 * @clk_gate_flags: gate-specific flags for this clock
568 * @lock: shared register lock for this clock
576 * clk_hw_register_gate_parent_hw - register a gate clock with the clock
578 * @dev: device that is registering this clock
579 * @name: name of this clock
581 * @flags: framework-specific flags for this clock
582 * @reg: register address to control gating of this clock
583 * @bit_idx: which bit in the register controls gating of this clock
584 * @clk_gate_flags: gate-specific flags for this clock
585 * @lock: shared register lock for this clock
593 * clk_hw_register_gate_parent_data - register a gate clock with the clock
595 * @dev: device that is registering this clock
596 * @name: name of this clock
598 * @flags: framework-specific flags for this clock
599 * @reg: register address to control gating of this clock
600 * @bit_idx: which bit in the register controls gating of this clock
601 * @clk_gate_flags: gate-specific flags for this clock
602 * @lock: shared register lock for this clock
610 * devm_clk_hw_register_gate - register a gate clock with the clock framework
611 * @dev: device that is registering this clock
612 * @name: name of this clock
613 * @parent_name: name of this clock's parent
614 * @flags: framework-specific flags for this clock
615 * @reg: register address to control gating of this clock
616 * @bit_idx: which bit in the register controls gating of this clock
617 * @clk_gate_flags: gate-specific flags for this clock
618 * @lock: shared register lock for this clock
626 * devm_clk_hw_register_gate_parent_data - register a gate clock with the
627 * clock framework
628 * @dev: device that is registering this clock
629 * @name: name of this clock
631 * @flags: framework-specific flags for this clock
632 * @reg: register address to control gating of this clock
633 * @bit_idx: which bit in the register controls gating of this clock
634 * @clk_gate_flags: gate-specific flags for this clock
635 * @lock: shared register lock for this clock
654 * struct clk_divider - adjustable divider clock
656 * @hw: handle between common and hardware-specific interfaces
663 * Clock with an adjustable divider affecting its output frequency. Implements
667 * CLK_DIVIDER_ONE_BASED - by default the divisor is the value read from the
671 * CLK_DIVIDER_POWER_OF_TWO - clock divisor is 2 raised to the value read from
673 * CLK_DIVIDER_ALLOW_ZERO - Allow zero divisors. For dividers which have
676 * zero divisor by not modifying their input clock
678 * CLK_DIVIDER_HIWORD_MASK - The divider settings are only in lower 16-bit
679 * of this register, and mask of divider bits are in higher 16-bit of this
680 * register. While setting the divider bits, higher 16-bit should also be
682 * CLK_DIVIDER_ROUND_CLOSEST - Makes the best calculated divider to be rounded
684 * CLK_DIVIDER_READ_ONLY - The divider settings are preconfigured and should
685 * not be changed by the clock framework.
686 * CLK_DIVIDER_MAX_AT_ZERO - For dividers which are like CLK_DIVIDER_ONE_BASED
689 * CLK_DIVIDER_BIG_ENDIAN - By default little endian register accesses are used
703 #define clk_div_mask(width) ((1 << (width)) - 1)
757 * clk_register_divider - register a divider clock with the clock framework
758 * @dev: device registering this clock
759 * @name: name of this clock
760 * @parent_name: name of clock's parent
761 * @flags: framework-specific flags
765 * @clk_divider_flags: divider-specific flags for this clock
766 * @lock: shared register lock for this clock
774 * clk_hw_register_divider - register a divider clock with the clock framework
775 * @dev: device registering this clock
776 * @name: name of this clock
777 * @parent_name: name of clock's parent
778 * @flags: framework-specific flags
782 * @clk_divider_flags: divider-specific flags for this clock
783 * @lock: shared register lock for this clock
791 * clk_hw_register_divider_parent_hw - register a divider clock with the clock
793 * @dev: device registering this clock
794 * @name: name of this clock
796 * @flags: framework-specific flags
800 * @clk_divider_flags: divider-specific flags for this clock
801 * @lock: shared register lock for this clock
810 * clk_hw_register_divider_parent_data - register a divider clock with the clock
812 * @dev: device registering this clock
813 * @name: name of this clock
815 * @flags: framework-specific flags
819 * @clk_divider_flags: divider-specific flags for this clock
820 * @lock: shared register lock for this clock
829 * clk_hw_register_divider_table - register a table based divider clock with
830 * the clock framework
831 * @dev: device registering this clock
832 * @name: name of this clock
833 * @parent_name: name of clock's parent
834 * @flags: framework-specific flags
838 * @clk_divider_flags: divider-specific flags for this clock
840 * @lock: shared register lock for this clock
849 * clk_hw_register_divider_table_parent_hw - register a table based divider
850 * clock with the clock framework
851 * @dev: device registering this clock
852 * @name: name of this clock
854 * @flags: framework-specific flags
858 * @clk_divider_flags: divider-specific flags for this clock
860 * @lock: shared register lock for this clock
870 * clk_hw_register_divider_table_parent_data - register a table based divider
871 * clock with the clock framework
872 * @dev: device registering this clock
873 * @name: name of this clock
875 * @flags: framework-specific flags
879 * @clk_divider_flags: divider-specific flags for this clock
881 * @lock: shared register lock for this clock
892 * devm_clk_hw_register_divider - register a divider clock with the clock framework
893 * @dev: device registering this clock
894 * @name: name of this clock
895 * @parent_name: name of clock's parent
896 * @flags: framework-specific flags
900 * @clk_divider_flags: divider-specific flags for this clock
901 * @lock: shared register lock for this clock
909 * devm_clk_hw_register_divider_parent_hw - register a divider clock with the clock framework
910 * @dev: device registering this clock
911 * @name: name of this clock
913 * @flags: framework-specific flags
917 * @clk_divider_flags: divider-specific flags for this clock
918 * @lock: shared register lock for this clock
928 * devm_clk_hw_register_divider_table - register a table based divider clock
929 * with the clock framework (devres variant)
930 * @dev: device registering this clock
931 * @name: name of this clock
932 * @parent_name: name of clock's parent
933 * @flags: framework-specific flags
937 * @clk_divider_flags: divider-specific flags for this clock
939 * @lock: shared register lock for this clock
953 * struct clk_mux - multiplexer clock
955 * @hw: handle between common and hardware-specific interfaces
960 * @flags: hardware-specific flags
963 * Clock with multiple selectable parents. Implements .get_parent, .set_parent
967 * CLK_MUX_INDEX_ONE - register index starts at 1, not 0
968 * CLK_MUX_INDEX_BIT - register index is a single bit (power of two)
969 * CLK_MUX_HIWORD_MASK - The mux settings are only in lower 16-bit of this
970 * register, and mask of mux bits are in higher 16-bit of this register.
971 * While setting the mux bits, higher 16-bit should also be updated to
973 * CLK_MUX_READ_ONLY - The mux registers can't be written, only read in the
975 * CLK_MUX_ROUND_CLOSEST - Use the parent rate that is closest to the desired
977 * CLK_MUX_BIG_ENDIAN - By default little endian register accesses are used for
1025 (flags), (reg), (shift), BIT((width)) - 1, \
1045 (shift), BIT((width)) - 1, (clk_mux_flags), \
1051 BIT((width)) - 1, (clk_mux_flags), NULL, (lock))
1057 BIT((width)) - 1, (clk_mux_flags), NULL, (lock))
1064 BIT((width)) - 1, (clk_mux_flags), table, (lock))
1069 (shift), BIT((width)) - 1, (clk_mux_flags), \
1076 (shift), BIT((width)) - 1, \
1084 BIT((width)) - 1, (clk_mux_flags), table, (lock))
1096 * struct clk_fixed_factor - fixed multiplier and divider clock
1098 * @hw: handle between common and hardware-specific interfaces
1101 * @acc: fixed accuracy in ppb
1104 * Clock with a fixed multiplier and divider. The output frequency is the
1105 * parent clock rate divided by div and multiplied by mult.
1109 * * CLK_FIXED_FACTOR_FIXED_ACCURACY - Use the value in @acc instead of the
1110 * parent clk accuracy.
1163 * struct clk_fractional_divider - adjustable fractional divider clock
1165 * @hw: handle between common and hardware-specific interfaces
1171 * @approximation: clk driver's callback for calculating the divider clock
1174 * Clock with adjustable fractional divider affecting its output frequency.
1177 * CLK_FRAC_DIVIDER_ZERO_BASED - by default the numerator and denominator
1181 * CLK_FRAC_DIVIDER_BIG_ENDIAN - By default little endian register accesses are
1184 * CLK_FRAC_DIVIDER_POWER_OF_TWO_PS - By default the resulting fraction might
1189 * caller's side the power-of-two capable prescaler exists.
1222 * struct clk_multiplier - adjustable multiplier clock
1224 * @hw: handle between common and hardware-specific interfaces
1230 * Clock with an adjustable multiplier affecting its output frequency.
1234 * CLK_MULTIPLIER_ZERO_BYPASS - By default, the multiplier is the value read
1236 * zeroing the output clock rate. If CLK_MULTIPLIER_ZERO_BYPASS is
1239 * CLK_MULTIPLIER_ROUND_CLOSEST - Makes the best calculated divider to be
1241 * CLK_MULTIPLIER_BIG_ENDIAN - By default little endian register accesses are
1263 * struct clk_composite - aggregate clock of mux, divider and gate clocks
1265 * @hw: handle between common and hardware-specific interfaces
1266 * @mux_hw: handle between composite and hardware-specific mux clock
1267 * @rate_hw: handle between composite and hardware-specific rate clock
1268 * @gate_hw: handle between composite and hardware-specific gate clock
1269 * @mux_ops: clock ops for mux
1270 * @rate_ops: clock ops for rate
1271 * @gate_ops: clock ops for gate
1385 dst->clk = src->clk; in __clk_hw_set_clk()
1386 dst->core = src->core; in __clk_hw_set_clk()
1410 * FIXME clock api without lock protection
1626 return ERR_PTR(-ENOENT); in of_clk_src_simple_get()
1631 return ERR_PTR(-ENOENT); in of_clk_hw_simple_get()
1636 return ERR_PTR(-ENOENT); in of_clk_src_onecell_get()
1641 return ERR_PTR(-ENOENT); in of_clk_hw_onecell_get()