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/linux-6.12.1/drivers/net/can/sja1000/
Dsja1000_isa.c1 // SPDX-License-Identifier: GPL-2.0-only
24 MODULE_DESCRIPTION("Socket-CAN driver for SJA1000 on the ISA bus");
35 static unsigned char cdr[MAXDEV] = {[0 ... (MAXDEV - 1)] = 0xff}; variable
36 static unsigned char ocr[MAXDEV] = {[0 ... (MAXDEV - 1)] = 0xff};
37 static int indirect[MAXDEV] = {[0 ... (MAXDEV - 1)] = -1};
38 static spinlock_t indirect_lock[MAXDEV]; /* lock for indirect access mode */
56 module_param_array(cdr, byte, NULL, 0444);
57 MODULE_PARM_DESC(cdr, "Clock divider register "
71 return readb(priv->reg_base + reg); in sja1000_isa_mem_read_reg()
77 writeb(val, priv->reg_base + reg); in sja1000_isa_mem_write_reg()
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Dsja1000_platform.c1 // SPDX-License-Identifier: GPL-2.0-only
28 MODULE_DESCRIPTION("Socket-CAN driver for SJA1000 on the platform bus");
43 return ioread8(priv->reg_base + reg); in sp_read_reg8()
48 iowrite8(val, priv->reg_base + reg); in sp_write_reg8()
53 return ioread8(priv->reg_base + reg * 2); in sp_read_reg16()
58 iowrite8(val, priv->reg_base + reg * 2); in sp_write_reg16()
63 return ioread8(priv->reg_base + reg * 4); in sp_read_reg32()
68 iowrite8(val, priv->reg_base + reg * 4); in sp_write_reg32()
73 struct technologic_priv *tp = priv->priv; in sp_technologic_read_reg16()
77 spin_lock_irqsave(&tp->io_lock, flags); in sp_technologic_read_reg16()
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Dplx_pci.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2008-2010 Pavel Cheblakov <P.B.Cheblakov@inp.nsk.su>
7 * Copyright (C) 2008 Markus Plessing <plessing@ems-wuensche.com>
8 * Copyright (C) 2008 Sebastian Haas <haas@ems-wuensche.com>
26 MODULE_DESCRIPTION("Socket-CAN driver for PLX90xx PCI-bridge cards with "
37 /* Pointer to device-dependent reset function */
71 * This means normal output mode, push-pull and the correct polarity.
79 * In the CDR register, you should set CBP to 1.
86 /* SJA1000 Control Register in the BasicCAN Mode */
89 /* States of some SJA1000 registers after hardware reset in the BasicCAN mode*/
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Dems_pcmcia.c1 // SPDX-License-Identifier: GPL-2.0-only
4 * Copyright (C) 2010 Markus Plessing <plessing@ems-wuensche.com>
22 MODULE_AUTHOR("Markus Plessing <plessing@ems-wuensche.com>");
23 MODULE_DESCRIPTION("Socket-CAN driver for EMS CPC-CARD cards");
43 * This means normal output mode , push-pull and the correct polarity.
48 * In the CDR register, you should set CBP to 1.
54 #define EMS_PCMCIA_MEM_SIZE 4096 /* Size of the remapped io-memory */
63 PCMCIA_DEVICE_PROD_ID123("EMS_T_W", "CPC-Card", "V2.0", 0xeab1ea23,
72 return readb(priv->reg_base + port); in ems_pcmcia_read_reg()
78 writeb(val, priv->reg_base + port); in ems_pcmcia_write_reg()
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Dkvaser_pci.c1 // SPDX-License-Identifier: GPL-2.0-only
7 * - Kvaser linux driver, version 4.72 BETA
8 * Copyright (C) 2002-2007 KVASER AB
10 * - Lincan driver, version 0.3.3, OCERA project
14 * - Socketcan SJA1000 drivers
16 * Copyright (c) 2002-2007 Volkswagen Group Electronic Research
35 MODULE_DESCRIPTION("Socket-CAN driver for KVASER PCAN PCI cards");
43 struct net_device *slave_dev[MAX_NO_OF_CHANNELS-1];
58 * This means normal output mode , push-pull and the correct polarity.
63 * In the CDR register, you should set CBP to 1.
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Dpeak_pcmcia.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2010-2012 Stephane Grosjean <s.grosjean@peak-system.com>
5 * CAN driver for PEAK-System PCAN-PC Card
7 * Copyright (C) 2006-2010 PEAK System-Technik GmbH
22 MODULE_AUTHOR("Stephane Grosjean <s.grosjean@peak-system.com>");
23 MODULE_DESCRIPTION("CAN driver for PEAK-System PCAN-PC Cards");
26 /* PEAK-System PCMCIA driver name */
117 * This means normal output mode, push-pull and the correct polarity.
122 * In the CDR register, you should set CBP to 1.
135 /* PCAN-PC Card private structure */
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Dems_pci.c1 // SPDX-License-Identifier: GPL-2.0-only
4 * Copyright (C) 2008 Markus Plessing <plessing@ems-wuensche.com>
5 * Copyright (C) 2008 Sebastian Haas <haas@ems-wuensche.com>
23 MODULE_AUTHOR("Sebastian Haas <support@ems-wuensche.com>");
24 MODULE_AUTHOR("Gerhard Uttenthaler <uttenthaler@ems-wuensche.com>");
25 MODULE_DESCRIPTION("Socket-CAN driver for EMS CPC-PCI/PCIe/104P CAN cards");
48 * PSB4610 PITA-2 bridge control registers
80 * This means normal output mode, push-pull and the correct polarity.
84 /* In the CDR register, you should set CBP to 1.
114 /* CPC-PCI v1 */
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Dsja1000.h2 * sja1000.h - Philips SJA1000 network device driver
7 * Copyright (c) 2002-2007 Volkswagen Group Electronic Research
56 /* SJA1000 registers - manual section 6.4 (Pelican Mode) */
78 /* Common registers - manual section 6.5 */
98 /* mode register */
159 /* the lower-layer is responsible for appropriate locking */
165 void *priv; /* for board-specific data */
172 u16 flags; /* custom mode flags */
174 u8 cdr; /* clock divider register */ member
Dtscan1.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * tscan1.c: driver for Technologic Systems TS-CAN1 PC104 boards
9 * - Getting started with TS-CAN1, Technologic Systems, Feb 2022
10 * https://docs.embeddedts.com/TS-CAN1
21 MODULE_DESCRIPTION("Driver for Technologic Systems TS-CAN1 PC104 boards");
41 /* PLD mode register SJA1000 IO enable bit */
68 return inb((unsigned long)priv->reg_base + reg); in tscan1_read()
74 outb(val, (unsigned long)priv->reg_base + reg); in tscan1_write()
77 /* Probe for a TS-CAN1 board with JP2:JP1 jumper setting ID */
87 return -EBUSY; in tscan1_probe()
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Dpeak_pci.c1 // SPDX-License-Identifier: GPL-2.0-only
4 * Copyright (C) 2012 Stephane Grosjean <s.grosjean@peak-system.com>
8 * Copyright (C) 2001-2006 PEAK System-Technik GmbH
19 #include <linux/i2c-algo-bit.h>
25 MODULE_AUTHOR("Stephane Grosjean <s.grosjean@peak-system.com>");
26 MODULE_DESCRIPTION("Socket-CAN driver for PEAK PCAN PCI family cards");
62 #define PEAK_PC_104P_DEVICE_ID 0x0006 /* PCAN-PC/104+ cards */
63 #define PEAK_PCI_104E_DEVICE_ID 0x0007 /* PCAN-PCI/104 Express cards */
65 #define PEAK_PCIE_OEM_ID 0x0009 /* PCAN-PCI Express OEM */
66 #define PEAK_PCIEC34_DEVICE_ID 0x000A /* PCAN-PCI Express 34 (one channel) */
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/linux-6.12.1/Documentation/devicetree/bindings/net/
Damd-xgbe.txt1 * AMD 10GbE driver (amd-xgbe)
4 - compatible: Should be "amd,xgbe-seattle-v1a"
5 - reg: Address and length of the register sets for the device
6 - MAC registers
7 - PCS registers
8 - SerDes Rx/Tx registers
9 - SerDes integration registers (1/2)
10 - SerDes integration registers (2/2)
11 - interrupts: Should contain the amd-xgbe interrupt(s). The first interrupt
13 amd,per-channel-interrupt property is specified, then one additional
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Dcortina.txt2 ---------------------------------------
7 devices, equipped with clock and data recovery (CDR) circuits. These
10 "ethernet-phy-id" compatible.
12 Since the driver only implements polling mode support, interrupts info
18 compatible = "ethernet-phy-id13e5.1002";
/linux-6.12.1/arch/arm64/boot/dts/amd/
Damd-seattle-xgbe-b.dtsi1 // SPDX-License-Identifier: GPL-2.0
9 compatible = "fixed-clock";
10 #clock-cells = <0>;
11 clock-frequency = <250000000>;
12 clock-output-names = "xgmacclk0_dma_250mhz";
16 compatible = "fixed-clock";
17 #clock-cells = <0>;
18 clock-frequency = <250000000>;
19 clock-output-names = "xgmacclk0_ptp_250mhz";
23 compatible = "fixed-clock";
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/linux-6.12.1/include/linux/can/platform/
Dsja1000.h1 /* SPDX-License-Identifier: GPL-2.0 */
10 #define CDR_PELICAN 0x80 /* PeliCAN mode */
33 u8 cdr; /* clock divider register */ member
/linux-6.12.1/Documentation/devicetree/bindings/media/i2c/
Dti,ds90ub960.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Texas Instruments DS90UB9XX Family FPD-Link Deserializer Hubs
10 - Tomi Valkeinen <tomi.valkeinen@ideasonboard.com>
13 The TI DS90UB9XX devices are FPD-Link video deserializers with I2C and GPIO
17 - $ref: /schemas/i2c/i2c-atr.yaml#
22 - ti,ds90ub960-q1
23 - ti,ds90ub9702-q1
33 clock-names:
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/linux-6.12.1/drivers/mtd/devices/
Ddocg3.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Handles the M-Systems DiskOnChip G3 chip
32 * As no specification is available from M-Systems/Sandisk, this drivers lacks
34 * - IPL write
40 * - a 1 byte Hamming code stored in the OOB for each page
41 * - a 7 bytes BCH code stored in the OOB for each page
43 * - BCH is in GF(2^14)
44 * - BCH is over data of 520 bytes (512 page + 7 page_info bytes
46 * - BCH can correct up to 4 bits (t = 4)
47 * - BCH syndroms are calculated in hardware, and checked in hardware as well
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/linux-6.12.1/drivers/scsi/mvsas/
Dmv_defs.h1 /* SPDX-License-Identifier: GPL-2.0-only */
7 * Copyright 2009-2011 Marvell. <yuxiangl@marvell.com>
28 /* driver compile-time configuration */
30 MVS_TX_RING_SZ = 1024, /* TX ring size (12-bit) */
31 MVS_RX_RING_SZ = 1024, /* RX ring size (12-bit) */
32 /* software requires power-of-2
44 MVS_SOC_CAN_QUEUE = MVS_SOC_SLOTS - 2,
79 /* MVS_GBL_PORT_TYPE */ /* shl for ports 1-3 */
93 MODE_SAS_PORT7_MASK = (1U << 7), /* port0 SAS(1), SATA(0) mode */
135 /* shl for ports 1-3 */
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Dmv_64xx.h1 /* SPDX-License-Identifier: GPL-2.0-only */
7 * Copyright 2009-2011 Marvell. <yuxiangl@marvell.com>
17 /* enhanced mode registers (BAR4) */
53 /* ports 1-3 follow after this */
56 /* ports 5-7 follow after this */
60 /* ports 1-3 follow after this */
62 /* ports 5-7 follow after this */
68 /* ports 1-3 follow after this */
71 /* ports 5-7 follow after this */
75 /* ports 1-3 follow after this */
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/linux-6.12.1/include/linux/bcma/
Dbcma_driver_pci.h1 /* SPDX-License-Identifier: GPL-2.0 */
113 #define BCMA_CORE_PCI_PLP_MODEREG 0x200 /* Mode */
162 #define BCMA_CORE_PCI_SERDES_RX_CDR 6 /* CDR */
163 #define BCMA_CORE_PCI_SERDES_RX_CDRBW 7 /* CDR BW */
205 /* PCIE Root Capability Register bits (Host mode only) */
237 #define pcicore_read16(pc, offset) bcma_read16((pc)->core, offset)
238 #define pcicore_read32(pc, offset) bcma_read32((pc)->core, offset)
239 #define pcicore_write16(pc, offset, val) bcma_write16((pc)->core, offset, val)
240 #define pcicore_write32(pc, offset, val) bcma_write32((pc)->core, offset, val)
256 return -ENOTSUPP; in bcma_core_pci_pcibios_map_irq()
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/linux-6.12.1/drivers/spi/
Dspi-sun4i.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright (C) 2012 - 2014 Allwinner Tech
7 * Maxime Ripard <maxime.ripard@free-electrons.com>
92 return readl(sspi->base_addr + reg); in sun4i_spi_read()
97 writel(value, sspi->base_addr + reg); in sun4i_spi_write()
138 while (len--) { in sun4i_spi_drain_fifo()
139 byte = readb(sspi->base_addr + SUN4I_RXDATA_REG); in sun4i_spi_drain_fifo()
140 if (sspi->rx_buf) in sun4i_spi_drain_fifo()
141 *sspi->rx_buf++ = byte; in sun4i_spi_drain_fifo()
151 cnt = SUN4I_FIFO_DEPTH - sun4i_spi_get_tx_fifo_count(sspi); in sun4i_spi_fill_fifo()
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Dspi-sun6i.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright (C) 2012 - 2014 Allwinner Tech
7 * Maxime Ripard <maxime.ripard@free-electrons.com>
119 return readl(sspi->base_addr + reg); in sun6i_spi_read()
124 writel(value, sspi->base_addr + reg); in sun6i_spi_write()
157 while (len--) { in sun6i_spi_drain_fifo()
158 byte = readb(sspi->base_addr + SUN6I_RXDATA_REG); in sun6i_spi_drain_fifo()
159 if (sspi->rx_buf) in sun6i_spi_drain_fifo()
160 *sspi->rx_buf++ = byte; in sun6i_spi_drain_fifo()
171 cnt = sspi->cfg->fifo_depth - sun6i_spi_get_tx_fifo_count(sspi); in sun6i_spi_fill_fifo()
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/linux-6.12.1/drivers/phy/samsung/
Dphy-samsung-ufs.c1 // SPDX-License-Identifier: GPL-2.0-only
20 #include <linux/soc/samsung/exynos-pmu.h>
22 #include "phy-samsung-ufs.h"
25 for (i = 0; i < (phy)->lane_cnt; i++)
27 for (; (cfg)->id; (cfg)++)
39 writel(cfg->val, (phy)->reg_pma + cfg->off_0); in samsung_ufs_phy_config()
42 if (cfg->id == PHY_TRSV_BLK) in samsung_ufs_phy_config()
43 writel(cfg->val, (phy)->reg_pma + cfg->off_1); in samsung_ufs_phy_config()
57 ufs_phy->reg_pma + PHY_APB_ADDR(PHY_PLL_LOCK_STATUS), in samsung_ufs_phy_wait_for_lock_acq()
60 dev_err(ufs_phy->dev, in samsung_ufs_phy_wait_for_lock_acq()
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Dphy-gs101-ufs.c1 // SPDX-License-Identifier: GPL-2.0-only
9 #include "phy-samsung-ufs.h"
103 /* Calibration for HS mode series A/B */
132 err = readl_poll_timeout(ufs_phy->reg_pma + off, in gs101_phy_wait_for_calibration()
137 dev_err(ufs_phy->dev, in gs101_phy_wait_for_calibration()
154 val = readl(ufs_phy->reg_pma + in gs101_phy_wait_for_cdr_lock()
162 writel(LN0_OVRD_RX_CDR_EN, ufs_phy->reg_pma + in gs101_phy_wait_for_cdr_lock()
165 ufs_phy->reg_pma + PHY_PMA_TRSV_ADDR(TRSV_REG222, lane)); in gs101_phy_wait_for_cdr_lock()
167 dev_err(ufs_phy->dev, "failed to get cdr lock\n"); in gs101_phy_wait_for_cdr_lock()
168 return -ETIMEDOUT; in gs101_phy_wait_for_cdr_lock()
/linux-6.12.1/drivers/phy/broadcom/
Dphy-brcm-sata.c1 // SPDX-License-Identifier: GPL-2.0-or-later
196 struct brcm_sata_phy *priv = port->phy_priv; in brcm_sata_ctrl_base()
199 switch (priv->version) { in brcm_sata_ctrl_base()
204 dev_err(priv->dev, "invalid phy version\n"); in brcm_sata_ctrl_base()
208 return priv->ctrl_base + (port->portnum * size); in brcm_sata_ctrl_base()
214 struct brcm_sata_phy *priv = port->phy_priv; in brcm_sata_phy_wr()
215 void __iomem *pcb_base = priv->phy_base; in brcm_sata_phy_wr()
218 if (priv->version == BRCM_SATA_PHY_STB_40NM) in brcm_sata_phy_wr()
219 bank += (port->portnum * SATA_PCB_REG_40NM_SPACE_SIZE); in brcm_sata_phy_wr()
221 pcb_base += (port->portnum * SATA_PCB_REG_28NM_SPACE_SIZE); in brcm_sata_phy_wr()
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/linux-6.12.1/drivers/phy/lantiq/
Dphy-lantiq-vrx200-pcie.c1 // SPDX-License-Identifier: GPL-2.0-only
8 * Copyright (C) 2009-2015 Lei Chuanhua <chuanhua.lei@lantiq.com>
27 #include <dt-bindings/phy/phy-lantiq-vrx200-pcie.h>
86 unsigned int mode; member
103 regmap_write(priv->phy_regmap, PCIE_PHY_PLL_A_CTRL1, 0x120e); in ltq_vrx200_pcie_phy_common_setup()
106 regmap_write(priv->phy_regmap, PCIE_PHY_PLL_A_CTRL2, 0x39d7); in ltq_vrx200_pcie_phy_common_setup()
107 regmap_write(priv->phy_regmap, PCIE_PHY_PLL_A_CTRL3, 0x0900); in ltq_vrx200_pcie_phy_common_setup()
110 regmap_write(priv->phy_regmap, PCIE_PHY_RX1_EI, 0x0004); in ltq_vrx200_pcie_phy_common_setup()
111 regmap_write(priv->phy_regmap, PCIE_PHY_RX1_A_CTRL, 0x6803); in ltq_vrx200_pcie_phy_common_setup()
113 regmap_update_bits(priv->phy_regmap, PCIE_PHY_TX1_CTRL1, in ltq_vrx200_pcie_phy_common_setup()
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