Lines Matching +full:cdr +full:- +full:mode
1 // SPDX-License-Identifier: GPL-2.0-only
8 * Copyright (C) 2009-2015 Lei Chuanhua <chuanhua.lei@lantiq.com>
27 #include <dt-bindings/phy/phy-lantiq-vrx200-pcie.h>
86 unsigned int mode; member
103 regmap_write(priv->phy_regmap, PCIE_PHY_PLL_A_CTRL1, 0x120e); in ltq_vrx200_pcie_phy_common_setup()
106 regmap_write(priv->phy_regmap, PCIE_PHY_PLL_A_CTRL2, 0x39d7); in ltq_vrx200_pcie_phy_common_setup()
107 regmap_write(priv->phy_regmap, PCIE_PHY_PLL_A_CTRL3, 0x0900); in ltq_vrx200_pcie_phy_common_setup()
110 regmap_write(priv->phy_regmap, PCIE_PHY_RX1_EI, 0x0004); in ltq_vrx200_pcie_phy_common_setup()
111 regmap_write(priv->phy_regmap, PCIE_PHY_RX1_A_CTRL, 0x6803); in ltq_vrx200_pcie_phy_common_setup()
113 regmap_update_bits(priv->phy_regmap, PCIE_PHY_TX1_CTRL1, in ltq_vrx200_pcie_phy_common_setup()
118 regmap_write(priv->phy_regmap, PCIE_PHY_TX1_A_CTRL2, 0x0706); in ltq_vrx200_pcie_phy_common_setup()
121 regmap_write(priv->phy_regmap, PCIE_PHY_TX1_CTRL3, 0x1fff); in ltq_vrx200_pcie_phy_common_setup()
124 regmap_write(priv->phy_regmap, PCIE_PHY_TX1_A_CTRL1, 0x0810); in ltq_vrx200_pcie_phy_common_setup()
127 regmap_update_bits(priv->phy_regmap, PCIE_PHY_TX2_A_CTRL2, 0x7f00, in ltq_vrx200_pcie_phy_common_setup()
131 regmap_write(priv->phy_regmap, PCIE_PHY_TX1_CTRL2, 0x2e00); in ltq_vrx200_pcie_phy_common_setup()
134 regmap_write(priv->phy_regmap, PCIE_PHY_TX2_CTRL2, 0x3096); in ltq_vrx200_pcie_phy_common_setup()
135 regmap_write(priv->phy_regmap, PCIE_PHY_TX2_A_CTRL2, 0x4707); in ltq_vrx200_pcie_phy_common_setup()
137 /* Reduced CDR BW to avoid glitches */ in ltq_vrx200_pcie_phy_common_setup()
138 regmap_write(priv->phy_regmap, PCIE_PHY_RX1_CDR, 0x0235); in ltq_vrx200_pcie_phy_common_setup()
145 regmap_update_bits(priv->phy_regmap, PCIE_PHY_PLL_CTRL3, in pcie_phy_36mhz_mode_setup()
148 regmap_update_bits(priv->phy_regmap, PCIE_PHY_PLL_CTRL3, in pcie_phy_36mhz_mode_setup()
151 regmap_update_bits(priv->phy_regmap, PCIE_PHY_PLL_CTRL2, in pcie_phy_36mhz_mode_setup()
155 regmap_update_bits(priv->phy_regmap, PCIE_PHY_PLL_CTRL2, in pcie_phy_36mhz_mode_setup()
159 regmap_update_bits(priv->phy_regmap, PCIE_PHY_PLL_A_CTRL3, in pcie_phy_36mhz_mode_setup()
163 regmap_update_bits(priv->phy_regmap, PCIE_PHY_PLL_A_CTRL2, in pcie_phy_36mhz_mode_setup()
167 regmap_write(priv->phy_regmap, PCIE_PHY_PLL_CTRL1, 0x38e4); in pcie_phy_36mhz_mode_setup()
169 regmap_update_bits(priv->phy_regmap, PCIE_PHY_PLL_CTRL2, in pcie_phy_36mhz_mode_setup()
175 regmap_write(priv->phy_regmap, PCIE_PHY_PLL_CTRL7, 0x0002); in pcie_phy_36mhz_mode_setup()
176 regmap_write(priv->phy_regmap, PCIE_PHY_PLL_CTRL6, 0x3a04); in pcie_phy_36mhz_mode_setup()
177 regmap_write(priv->phy_regmap, PCIE_PHY_PLL_CTRL5, 0xfae3); in pcie_phy_36mhz_mode_setup()
178 regmap_write(priv->phy_regmap, PCIE_PHY_PLL_CTRL4, 0x1b72); in pcie_phy_36mhz_mode_setup()
187 ret = regmap_read_poll_timeout(priv->phy_regmap, PCIE_PHY_PLL_STATUS, in ltq_vrx200_pcie_phy_wait_for_pll()
191 dev_err(priv->dev, "PLL Link timeout, PLL status = 0x%04x\n", in ltq_vrx200_pcie_phy_wait_for_pll()
220 regmap_update_bits(priv->phy_regmap, slices[i].reg, in ltq_vrx200_pcie_phy_apply_workarounds()
226 regmap_update_bits(priv->phy_regmap, slices[i].reg, in ltq_vrx200_pcie_phy_apply_workarounds()
232 regmap_write(priv->phy_regmap, PCIE_PHY_TX2_MOD1, 0x1ffe); in ltq_vrx200_pcie_phy_apply_workarounds()
233 regmap_write(priv->phy_regmap, PCIE_PHY_TX2_MOD2, 0xfffe); in ltq_vrx200_pcie_phy_apply_workarounds()
234 regmap_write(priv->phy_regmap, PCIE_PHY_TX2_MOD3, 0x0601); in ltq_vrx200_pcie_phy_apply_workarounds()
236 regmap_write(priv->phy_regmap, PCIE_PHY_TX2_MOD3, 0x0001); in ltq_vrx200_pcie_phy_apply_workarounds()
239 regmap_write(priv->phy_regmap, PCIE_PHY_TX1_MOD1, 0x1ffe); in ltq_vrx200_pcie_phy_apply_workarounds()
240 regmap_write(priv->phy_regmap, PCIE_PHY_TX1_MOD2, 0xfffe); in ltq_vrx200_pcie_phy_apply_workarounds()
241 regmap_write(priv->phy_regmap, PCIE_PHY_TX1_MOD3, 0x0601); in ltq_vrx200_pcie_phy_apply_workarounds()
243 regmap_write(priv->phy_regmap, PCIE_PHY_TX1_MOD3, 0x0001); in ltq_vrx200_pcie_phy_apply_workarounds()
252 if (of_device_is_big_endian(priv->dev->of_node)) in ltq_vrx200_pcie_phy_init()
253 regmap_update_bits(priv->rcu_regmap, in ltq_vrx200_pcie_phy_init()
254 priv->rcu_ahb_endian_offset, in ltq_vrx200_pcie_phy_init()
255 priv->rcu_ahb_endian_big_endian_mask, in ltq_vrx200_pcie_phy_init()
256 priv->rcu_ahb_endian_big_endian_mask); in ltq_vrx200_pcie_phy_init()
258 regmap_update_bits(priv->rcu_regmap, in ltq_vrx200_pcie_phy_init()
259 priv->rcu_ahb_endian_offset, in ltq_vrx200_pcie_phy_init()
260 priv->rcu_ahb_endian_big_endian_mask, 0x0); in ltq_vrx200_pcie_phy_init()
262 ret = reset_control_assert(priv->phy_reset); in ltq_vrx200_pcie_phy_init()
268 ret = reset_control_deassert(priv->phy_reset); in ltq_vrx200_pcie_phy_init()
274 ret = reset_control_deassert(priv->pcie_reset); in ltq_vrx200_pcie_phy_init()
284 reset_control_assert(priv->phy_reset); in ltq_vrx200_pcie_phy_init()
294 ret = reset_control_assert(priv->pcie_reset); in ltq_vrx200_pcie_phy_exit()
298 ret = reset_control_assert(priv->phy_reset); in ltq_vrx200_pcie_phy_exit()
311 ret = clk_prepare_enable(priv->pdi_clk); in ltq_vrx200_pcie_phy_power_on()
321 ret = clk_prepare_enable(priv->phy_clk); in ltq_vrx200_pcie_phy_power_on()
335 clk_disable_unprepare(priv->phy_clk); in ltq_vrx200_pcie_phy_power_on()
337 clk_disable_unprepare(priv->pdi_clk); in ltq_vrx200_pcie_phy_power_on()
346 clk_disable_unprepare(priv->phy_clk); in ltq_vrx200_pcie_phy_power_off()
347 clk_disable_unprepare(priv->pdi_clk); in ltq_vrx200_pcie_phy_power_off()
364 unsigned int mode; in ltq_vrx200_pcie_phy_xlate() local
366 if (args->args_count != 1) { in ltq_vrx200_pcie_phy_xlate()
368 return ERR_PTR(-EINVAL); in ltq_vrx200_pcie_phy_xlate()
371 mode = args->args[0]; in ltq_vrx200_pcie_phy_xlate()
373 switch (mode) { in ltq_vrx200_pcie_phy_xlate()
375 priv->mode = mode; in ltq_vrx200_pcie_phy_xlate()
383 dev_err(dev, "PHY mode not implemented yet: %u\n", mode); in ltq_vrx200_pcie_phy_xlate()
384 return ERR_PTR(-EINVAL); in ltq_vrx200_pcie_phy_xlate()
387 dev_err(dev, "invalid PHY mode %u\n", mode); in ltq_vrx200_pcie_phy_xlate()
388 return ERR_PTR(-EINVAL); in ltq_vrx200_pcie_phy_xlate()
391 return priv->phy; in ltq_vrx200_pcie_phy_xlate()
403 struct device *dev = &pdev->dev; in ltq_vrx200_pcie_phy_probe()
410 return -ENOMEM; in ltq_vrx200_pcie_phy_probe()
416 priv->phy_regmap = devm_regmap_init_mmio(dev, base, ®map_config); in ltq_vrx200_pcie_phy_probe()
417 if (IS_ERR(priv->phy_regmap)) in ltq_vrx200_pcie_phy_probe()
418 return PTR_ERR(priv->phy_regmap); in ltq_vrx200_pcie_phy_probe()
420 priv->rcu_regmap = syscon_regmap_lookup_by_phandle(dev->of_node, in ltq_vrx200_pcie_phy_probe()
422 if (IS_ERR(priv->rcu_regmap)) in ltq_vrx200_pcie_phy_probe()
423 return PTR_ERR(priv->rcu_regmap); in ltq_vrx200_pcie_phy_probe()
425 ret = device_property_read_u32(dev, "lantiq,rcu-endian-offset", in ltq_vrx200_pcie_phy_probe()
426 &priv->rcu_ahb_endian_offset); in ltq_vrx200_pcie_phy_probe()
429 "failed to parse the 'lantiq,rcu-endian-offset' property\n"); in ltq_vrx200_pcie_phy_probe()
433 ret = device_property_read_u32(dev, "lantiq,rcu-big-endian-mask", in ltq_vrx200_pcie_phy_probe()
434 &priv->rcu_ahb_endian_big_endian_mask); in ltq_vrx200_pcie_phy_probe()
437 "failed to parse the 'lantiq,rcu-big-endian-mask' property\n"); in ltq_vrx200_pcie_phy_probe()
441 priv->pdi_clk = devm_clk_get(dev, "pdi"); in ltq_vrx200_pcie_phy_probe()
442 if (IS_ERR(priv->pdi_clk)) in ltq_vrx200_pcie_phy_probe()
443 return PTR_ERR(priv->pdi_clk); in ltq_vrx200_pcie_phy_probe()
445 priv->phy_clk = devm_clk_get(dev, "phy"); in ltq_vrx200_pcie_phy_probe()
446 if (IS_ERR(priv->phy_clk)) in ltq_vrx200_pcie_phy_probe()
447 return PTR_ERR(priv->phy_clk); in ltq_vrx200_pcie_phy_probe()
449 priv->phy_reset = devm_reset_control_get_exclusive(dev, "phy"); in ltq_vrx200_pcie_phy_probe()
450 if (IS_ERR(priv->phy_reset)) in ltq_vrx200_pcie_phy_probe()
451 return PTR_ERR(priv->phy_reset); in ltq_vrx200_pcie_phy_probe()
453 priv->pcie_reset = devm_reset_control_get_shared(dev, "pcie"); in ltq_vrx200_pcie_phy_probe()
454 if (IS_ERR(priv->pcie_reset)) in ltq_vrx200_pcie_phy_probe()
455 return PTR_ERR(priv->pcie_reset); in ltq_vrx200_pcie_phy_probe()
457 priv->dev = dev; in ltq_vrx200_pcie_phy_probe()
459 priv->phy = devm_phy_create(dev, dev->of_node, in ltq_vrx200_pcie_phy_probe()
461 if (IS_ERR(priv->phy)) { in ltq_vrx200_pcie_phy_probe()
463 return PTR_ERR(priv->phy); in ltq_vrx200_pcie_phy_probe()
466 phy_set_drvdata(priv->phy, priv); in ltq_vrx200_pcie_phy_probe()
476 { .compatible = "lantiq,vrx200-pcie-phy", },
477 { .compatible = "lantiq,arx300-pcie-phy", },
485 .name = "ltq-vrx200-pcie-phy",