Lines Matching +full:cdr +full:- +full:mode
1 /* SPDX-License-Identifier: GPL-2.0-only */
7 * Copyright 2009-2011 Marvell. <yuxiangl@marvell.com>
28 /* driver compile-time configuration */
30 MVS_TX_RING_SZ = 1024, /* TX ring size (12-bit) */
31 MVS_RX_RING_SZ = 1024, /* RX ring size (12-bit) */
32 /* software requires power-of-2
44 MVS_SOC_CAN_QUEUE = MVS_SOC_SLOTS - 2,
79 /* MVS_GBL_PORT_TYPE */ /* shl for ports 1-3 */
93 MODE_SAS_PORT7_MASK = (1U << 7), /* port0 SAS(1), SATA(0) mode */
135 /* shl for ports 1-3 */
150 TXQ_MODE_I = (1U << 28), /* mode: 0=target,1=initiator */
173 MCH_PRD_LEN_SHIFT = 16, /* 16-bit PRD table len */
190 MCH_PASSTHRU = (1U << 12), /* pass-through (SSP) */
209 /* MVS_Px_SER_CTLSTAT (per-phy control) */
216 /* MVS_Px_INT_STAT, MVS_Px_INT_MASK (per-phy events) */
224 PHYEV_POOF = (1U << 12), /* phy ready from 1 -> 0 */
245 PCS_SELF_CLEAR = (1U << 5), /* self-clearing int mode */
247 PCS_CMD_STOP_ERR = (1U << 3), /* cmd stop-on-err enable */
274 PHY_MODE6_FC_ORDER = (1U << 26), /* Fibre Channel Mode Order*/
281 PHY_MODE6_FREEZE_LOOP = (1U << 12), /* Freeze Rx CDR Loop */
282 PHY_MODE6_INT_RXFOFFS = (1U << 3), /* Rx CDR Freq Loop Enable */
283 PHY_MODE6_FRC_RXFOFFS = (1U << 2), /* Initial Rx CDR Offset */
284 PHY_MODE6_STAU_0D8 = (1U << 1), /* Rx CDR Freq Loop Saturate */
298 PHYR_SATA_SIG0 = 0x20, /*port SATA signature FIS(Byte 0-3) */
299 PHYR_SATA_SIG1 = 0x24, /*port SATA signature FIS(Byte 4-7) */
300 PHYR_SATA_SIG2 = 0x28, /*port SATA signature FIS(Byte 8-11) */
301 PHYR_SATA_SIG3 = 0x2c, /*port SATA signature FIS(Byte 12-15) */
371 CMD_PHY_MODE_21 = 0x1B8, /* Phy Mode 21 */
372 CMD_SL_MODE0 = 0x1BC, /* SL Mode 0 */
373 CMD_SL_MODE1 = 0x1C0, /* SL Mode 1 */