| /linux-6.12.1/Documentation/devicetree/bindings/pci/ |
| D | xlnx,axi-pcie-host.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/xlnx,axi-pcie-host.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Xilinx AXI PCIe Root Port Bridge
10 - Thippeswamy Havalige <thippeswamy.havalige@amd.com>
13 - $ref: /schemas/pci/pci-host-bridge.yaml#
17 const: xlnx,axi-pcie-host-1.00.a
20 maxItems: 1
23 maxItems: 1
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| D | rockchip,rk3399-pcie.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/rockchip,rk3399-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Rockchip AXI PCIe Root Port Bridge Host
10 - Shawn Lin <shawn.lin@rock-chips.com>
13 - $ref: /schemas/pci/pci-host-bridge.yaml#
14 - $ref: rockchip,rk3399-pcie-common.yaml#
18 const: rockchip,rk3399-pcie
22 reg-names:
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| D | host-generic-pci.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/host-generic-pci.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Generic PCI host controller
10 - Will Deacon <will@kernel.org>
13 Firmware-initialised PCI host controllers and PCI emulations, such as the
14 virtio-pci implementations found in kvmtool and other para-virtualised
21 Configuration Space is assumed to be memory-mapped (as opposed to being
26 For CAM, this 24-bit offset is:
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| D | starfive,jh7110-pcie.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/starfive,jh7110-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: StarFive JH7110 PCIe host controller
10 - Kevin Xie <kevin.xie@starfivetech.com>
13 - $ref: plda,xpressrich3-axi-common.yaml#
17 const: starfive,jh7110-pcie
21 - description: NOC bus clock
22 - description: Transport layer clock
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| D | qcom,pcie.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/qcom,pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Bjorn Andersson <bjorn.andersson@linaro.org>
11 - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
14 Qualcomm PCIe root complex controller is based on the Synopsys DesignWare
15 PCIe IP.
20 - enum:
21 - qcom,pcie-apq8064
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| D | brcm,iproc-pcie.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/brcm,iproc-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Broadcom iProc PCIe controller with the platform bus interface
10 - Ray Jui <ray.jui@broadcom.com>
11 - Scott Branden <scott.branden@broadcom.com>
14 - $ref: /schemas/pci/pci-host-bridge.yaml#
19 - enum:
22 - brcm,iproc-pcie
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| D | snps,dw-pcie-common.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/snps,dw-pcie-common.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Synopsys DWC PCIe RP/EP controller
10 - Jingoo Han <jingoohan1@gmail.com>
11 - Gustavo Pimentel <gustavo.pimentel@synopsys.com>
14 Generic Synopsys DesignWare PCIe Root Port and Endpoint controller
22 DWC PCIe CSR space is normally accessed over the dedicated Data Bus
23 Interface - DBI. In accordance with the reference manual the register
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| D | plda,xpressrich3-axi-common.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/plda,xpressrich3-axi-common.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: PLDA XpressRICH PCIe host common properties
10 - Daire McNamara <daire.mcnamara@microchip.com>
11 - Kevin Xie <kevin.xie@starfivetech.com>
14 Generic PLDA XpressRICH PCIe host common properties.
17 - $ref: /schemas/pci/pci-host-bridge.yaml#
23 reg-names:
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| D | cdns-pcie-host.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/cdns-pcie-host.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Cadence PCIe Host
10 - Tom Joseph <tjoseph@cadence.com>
13 - $ref: /schemas/pci/pci-host-bridge.yaml#
14 - $ref: cdns-pcie.yaml#
17 cdns,max-outbound-regions:
20 minimum: 1
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| D | snps,dw-pcie.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/pci/snps,dw-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Synopsys DesignWare PCIe interface
10 - Jingoo Han <jingoohan1@gmail.com>
11 - Gustavo Pimentel <gustavo.pimentel@synopsys.com>
14 Synopsys DesignWare PCIe host controller
16 # Please create a separate DT-schema for your DWC PCIe Root Port controller
17 # and make sure it's assigned with the vendor-specific compatible string.
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| D | ti-pci.txt | 3 PCIe DesignWare Controller
4 - compatible: Should be "ti,dra7-pcie" for RC (deprecated)
5 Should be "ti,dra7-pcie-ep" for EP (deprecated)
6 Should be "ti,dra746-pcie-rc" for dra74x/dra76 in RC mode
7 Should be "ti,dra746-pcie-ep" for dra74x/dra76 in EP mode
8 Should be "ti,dra726-pcie-rc" for dra72x in RC mode
9 Should be "ti,dra726-pcie-ep" for dra72x in EP mode
10 - phys : list of PHY specifiers (used by generic PHY framework)
11 - phy-names : must be "pcie-phy0", "pcie-phy1", "pcie-phyN".. based on the
13 - ti,hwmods : Name of the hwmod associated to the pcie, "pcie<X>",
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| D | microchip,pcie-host.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/microchip,pcie-host.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Microchip PCIe Root Port Bridge Controller
10 - Daire McNamara <daire.mcnamara@microchip.com>
13 - $ref: plda,xpressrich3-axi-common.yaml#
14 - $ref: /schemas/interrupt-controller/msi-controller.yaml#
18 const: microchip,pcie-host-1.0 # PolarFire
30 minItems: 1
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| /linux-6.12.1/drivers/pci/controller/ |
| D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0
7 tristate "Aardvark PCIe controller"
13 Add support for Aardvark 64bit PCIe Host Controller. This
18 tristate "Altera PCIe controller"
21 Say Y here if you want to enable PCIe controller support on Altera
25 tristate "Altera PCIe MSI feature"
29 Say Y here if you want PCIe MSI support for the Altera FPGA.
38 tristate "Apple PCIe controller"
44 Say Y here if you want to enable PCIe controller support on Apple
45 system-on-chips, like the Apple M1. This is required for the USB
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| D | pcie-iproc.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2014 Hauke Mehrtens <hauke@hauke-m.de>
9 #include <linux/pci-ecam.h>
17 #include <linux/irqchip/arm-gic-v3.h>
24 #include "pcie-iproc.h"
28 #define EP_MODE_SURVIVE_PERST_SHIFT 1
43 #define CFG_ADDR_CFG_TYPE_1 1
56 #define CFG_RD_UR 1
73 #define OARR_SIZE_CFG_SHIFT 1
91 * struct iproc_pcie_ob_map - iProc PCIe outbound mapping controller-specific
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| D | pcie-xilinx.c | 1 // SPDX-License-Identifier: GPL-2.0+
3 * PCIe host controller driver for Xilinx AXI PCIe Bridge
5 * Copyright (c) 2012 - 2014 Xilinx, Inc.
7 * Based on the Tegra PCIe driver
9 * Bits taken from Synopsys DesignWare Host controller driver and
10 * ARM PCI Host generic driver.
24 #include <linux/pci-ecam.h>
43 #define XILINX_PCIE_INTR_ECRC_ERR BIT(1)
70 /* Root Port Interrupt FIFO Read Register 1 definitions */
94 * struct xilinx_pcie - PCIe port information
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| D | pcie-rockchip.c | 1 // SPDX-License-Identifier: GPL-2.0+
3 * Rockchip AXI PCIe host controller driver
7 * Author: Shawn Lin <shawn.lin@rock-chips.com>
8 * Wenrui Li <wenrui.li@rock-chips.com>
10 * Bits taken from Synopsys DesignWare Host controller driver and
11 * ARM PCI Host generic driver.
25 #include "pcie-rockchip.h"
29 struct device *dev = rockchip->dev; in rockchip_pcie_parse_dt()
31 struct device_node *node = dev->of_node; in rockchip_pcie_parse_dt()
35 if (rockchip->is_rc) { in rockchip_pcie_parse_dt()
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| /linux-6.12.1/drivers/pci/controller/mobiveil/ |
| D | pcie-mobiveil.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * PCIe host controller driver for Mobiveil PCIe Host controller
18 #include "pcie-mobiveil.h"
21 * mobiveil_pcie_sel_page - routine to access paged register
28 static void mobiveil_pcie_sel_page(struct mobiveil_pcie *pcie, u8 pg_idx) in mobiveil_pcie_sel_page() argument
32 val = readl(pcie->csr_axi_slave_base + PAB_CTRL); in mobiveil_pcie_sel_page()
36 writel(val, pcie->csr_axi_slave_base + PAB_CTRL); in mobiveil_pcie_sel_page()
39 static void __iomem *mobiveil_pcie_comp_addr(struct mobiveil_pcie *pcie, in mobiveil_pcie_comp_addr() argument
44 mobiveil_pcie_sel_page(pcie, 0); in mobiveil_pcie_comp_addr()
45 return pcie->csr_axi_slave_base + off; in mobiveil_pcie_comp_addr()
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| /linux-6.12.1/drivers/pci/controller/plda/ |
| D | pcie-plda.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
3 * PLDA PCIe host controller driver
12 /* PCIe Bridge Phy Regs */
14 #define RP_ENABLE 1
32 #define DMA_END_ENGINE_1_SHIFT 1
81 /* PCIe Master table init defines */
84 #define ATR0_PCIE_ATR_SIZE_SHIFT 1
90 /* PCIe AXI slave table init defines */
92 #define ATR_SIZE_SHIFT 1
93 #define ATR_IMPL_ENABLE 1
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| D | pcie-microchip-host.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Microchip AXI PCIe Bridge host controller driver
5 * Copyright (c) 2018 - 2020 Microchip Corporation. All rights reserved.
18 #include <linux/pci-ecam.h>
22 #include "pcie-plda.h"
24 /* PCIe Bridge Phy and Controller Phy offsets */
31 /* PCIe Controller Phy Regs */
52 #define ECC_CONTROL_TX_RAM_INJ_ERROR_1 BIT(1)
73 #define PCIE_EVENT_INT_HOTRST_EXIT_INT BIT(1)
83 /* PCIe Config space MSI capability structure */
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| /linux-6.12.1/arch/mips/boot/dts/img/ |
| D | boston.dts | 1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include <dt-bindings/clock/boston-clock.h>
5 #include <dt-bindings/gpio/gpio.h>
6 #include <dt-bindings/interrupt-controller/irq.h>
7 #include <dt-bindings/interrupt-controller/mips-gic.h>
10 #address-cells = <1>;
11 #size-cells = <1>;
15 stdout-path = "uart0:115200";
23 #address-cells = <1>;
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| /linux-6.12.1/Documentation/devicetree/bindings/ata/ |
| D | apm-xgene.txt | 1 * APM X-Gene 6.0 Gb/s SATA host controller nodes
3 SATA host controller nodes are defined to describe on-chip Serial ATA
7 - compatible : Shall contain:
8 * "apm,xgene-ahci"
9 - reg : First memory resource shall be the AHCI memory
11 Second memory resource shall be the host controller
13 Third memory resource shall be the host controller
15 4th memory resource shall be the host controller
16 AXI memory resource.
17 5th optional memory resource shall be the host
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| /linux-6.12.1/include/dt-bindings/memory/ |
| D | tegra186-mc.h | 117 /* PCIE reads */
119 /* High-definition audio (HDA) reads */
121 /* Host channel data reads */
126 /* Reads from Cortex-A9 4 CPU cores via the L2 cache */
129 /* PCIE writes */
131 /* High-definition audio (HDA) writes */
133 /* Writes from Cortex-A9 4 CPU cores via the L2 cache */
199 /* 3D, ltcx reads instance 1 */
201 /* 3D, ltcx writes instance 1 */
203 /* AXI Switch read client */
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| /linux-6.12.1/drivers/pci/controller/cadence/ |
| D | pcie-cadence-host.c | 1 // SPDX-License-Identifier: GPL-2.0
3 // Cadence PCIe host controller driver.
4 // Author: Cyrille Pitchen <cyrille.pitchen@free-electrons.com>
13 #include "pcie-cadence.h"
33 struct cdns_pcie *pcie = &rc->pcie; in cdns_pci_map_bus() local
34 unsigned int busn = bus->number; in cdns_pci_map_bus()
46 return pcie->reg_base + (where & 0xfff); in cdns_pci_map_bus()
49 if (!(cdns_pcie_readl(pcie, CDNS_PCIE_LM_BASE) & 0x1)) in cdns_pci_map_bus()
51 /* Clear AXI link-down status */ in cdns_pci_map_bus()
52 cdns_pcie_writel(pcie, CDNS_PCIE_AT_LINKDOWN, 0x0); in cdns_pci_map_bus()
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| /linux-6.12.1/drivers/pci/controller/dwc/ |
| D | pcie-qcom-ep.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Qualcomm PCIe Endpoint controller driver
18 #include <linux/phy/pcie.h>
27 #include "pcie-designware.h"
28 #include "pcie-qcom-common.h"
65 #define PARF_INT_ALL_LINK_DOWN BIT(1)
88 #define PARF_DEBUG_INT_PM_DSTATE_CHANGE BIT(1)
93 #define WR_NO_SNOOP_OVERIDE_EN BIT(1)
100 #define PARF_PM_CTRL_REQ_EXIT_L1 BIT(1)
105 #define PARF_MSTR_AXI_CLK_EN BIT(1)
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| /linux-6.12.1/arch/arm/boot/dts/qcom/ |
| D | qcom-ipq8064.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include <dt-bindings/interrupt-controller/arm-gic.h>
5 #include <dt-bindings/mfd/qcom-rpm.h>
6 #include <dt-bindings/clock/qcom,rpmcc.h>
7 #include <dt-bindings/clock/qcom,gcc-ipq806x.h>
8 #include <dt-bindings/clock/qcom,lcc-ipq806x.h>
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/reset/qcom,gcc-ipq806x.h>
11 #include <dt-bindings/soc/qcom,gsbi.h>
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