1// SPDX-License-Identifier: GPL-2.0 2/dts-v1/; 3 4#include <dt-bindings/interrupt-controller/arm-gic.h> 5#include <dt-bindings/mfd/qcom-rpm.h> 6#include <dt-bindings/clock/qcom,rpmcc.h> 7#include <dt-bindings/clock/qcom,gcc-ipq806x.h> 8#include <dt-bindings/clock/qcom,lcc-ipq806x.h> 9#include <dt-bindings/gpio/gpio.h> 10#include <dt-bindings/reset/qcom,gcc-ipq806x.h> 11#include <dt-bindings/soc/qcom,gsbi.h> 12#include <dt-bindings/interrupt-controller/arm-gic.h> 13 14/ { 15 #address-cells = <1>; 16 #size-cells = <1>; 17 model = "Qualcomm IPQ8064"; 18 compatible = "qcom,ipq8064"; 19 interrupt-parent = <&intc>; 20 21 cpus { 22 #address-cells = <1>; 23 #size-cells = <0>; 24 25 cpu0: cpu@0 { 26 compatible = "qcom,krait"; 27 enable-method = "qcom,kpss-acc-v1"; 28 device_type = "cpu"; 29 reg = <0>; 30 next-level-cache = <&L2>; 31 qcom,acc = <&acc0>; 32 qcom,saw = <&saw0>; 33 }; 34 35 cpu1: cpu@1 { 36 compatible = "qcom,krait"; 37 enable-method = "qcom,kpss-acc-v1"; 38 device_type = "cpu"; 39 reg = <1>; 40 next-level-cache = <&L2>; 41 qcom,acc = <&acc1>; 42 qcom,saw = <&saw1>; 43 }; 44 45 L2: l2-cache { 46 compatible = "cache"; 47 cache-level = <2>; 48 cache-unified; 49 }; 50 }; 51 52 thermal-zones { 53 sensor0-thermal { 54 polling-delay-passive = <0>; 55 polling-delay = <0>; 56 thermal-sensors = <&tsens 0>; 57 58 trips { 59 cpu-critical { 60 temperature = <105000>; 61 hysteresis = <2000>; 62 type = "critical"; 63 }; 64 65 cpu-hot { 66 temperature = <95000>; 67 hysteresis = <2000>; 68 type = "hot"; 69 }; 70 }; 71 }; 72 73 sensor1-thermal { 74 polling-delay-passive = <0>; 75 polling-delay = <0>; 76 thermal-sensors = <&tsens 1>; 77 78 trips { 79 cpu-critical { 80 temperature = <105000>; 81 hysteresis = <2000>; 82 type = "critical"; 83 }; 84 85 cpu-hot { 86 temperature = <95000>; 87 hysteresis = <2000>; 88 type = "hot"; 89 }; 90 }; 91 }; 92 93 sensor2-thermal { 94 polling-delay-passive = <0>; 95 polling-delay = <0>; 96 thermal-sensors = <&tsens 2>; 97 98 trips { 99 cpu-critical { 100 temperature = <105000>; 101 hysteresis = <2000>; 102 type = "critical"; 103 }; 104 105 cpu-hot { 106 temperature = <95000>; 107 hysteresis = <2000>; 108 type = "hot"; 109 }; 110 }; 111 }; 112 113 sensor3-thermal { 114 polling-delay-passive = <0>; 115 polling-delay = <0>; 116 thermal-sensors = <&tsens 3>; 117 118 trips { 119 cpu-critical { 120 temperature = <105000>; 121 hysteresis = <2000>; 122 type = "critical"; 123 }; 124 125 cpu-hot { 126 temperature = <95000>; 127 hysteresis = <2000>; 128 type = "hot"; 129 }; 130 }; 131 }; 132 133 sensor4-thermal { 134 polling-delay-passive = <0>; 135 polling-delay = <0>; 136 thermal-sensors = <&tsens 4>; 137 138 trips { 139 cpu-critical { 140 temperature = <105000>; 141 hysteresis = <2000>; 142 type = "critical"; 143 }; 144 145 cpu-hot { 146 temperature = <95000>; 147 hysteresis = <2000>; 148 type = "hot"; 149 }; 150 }; 151 }; 152 153 sensor5-thermal { 154 polling-delay-passive = <0>; 155 polling-delay = <0>; 156 thermal-sensors = <&tsens 5>; 157 158 trips { 159 cpu-critical { 160 temperature = <105000>; 161 hysteresis = <2000>; 162 type = "critical"; 163 }; 164 165 cpu-hot { 166 temperature = <95000>; 167 hysteresis = <2000>; 168 type = "hot"; 169 }; 170 }; 171 }; 172 173 sensor6-thermal { 174 polling-delay-passive = <0>; 175 polling-delay = <0>; 176 thermal-sensors = <&tsens 6>; 177 178 trips { 179 cpu-critical { 180 temperature = <105000>; 181 hysteresis = <2000>; 182 type = "critical"; 183 }; 184 185 cpu-hot { 186 temperature = <95000>; 187 hysteresis = <2000>; 188 type = "hot"; 189 }; 190 }; 191 }; 192 193 sensor7-thermal { 194 polling-delay-passive = <0>; 195 polling-delay = <0>; 196 thermal-sensors = <&tsens 7>; 197 198 trips { 199 cpu-critical { 200 temperature = <105000>; 201 hysteresis = <2000>; 202 type = "critical"; 203 }; 204 205 cpu-hot { 206 temperature = <95000>; 207 hysteresis = <2000>; 208 type = "hot"; 209 }; 210 }; 211 }; 212 213 sensor8-thermal { 214 polling-delay-passive = <0>; 215 polling-delay = <0>; 216 thermal-sensors = <&tsens 8>; 217 218 trips { 219 cpu-critical { 220 temperature = <105000>; 221 hysteresis = <2000>; 222 type = "critical"; 223 }; 224 225 cpu-hot { 226 temperature = <95000>; 227 hysteresis = <2000>; 228 type = "hot"; 229 }; 230 }; 231 }; 232 233 sensor9-thermal { 234 polling-delay-passive = <0>; 235 polling-delay = <0>; 236 thermal-sensors = <&tsens 9>; 237 238 trips { 239 cpu-critical { 240 temperature = <105000>; 241 hysteresis = <2000>; 242 type = "critical"; 243 }; 244 245 cpu-hot { 246 temperature = <95000>; 247 hysteresis = <2000>; 248 type = "hot"; 249 }; 250 }; 251 }; 252 253 sensor10-thermal { 254 polling-delay-passive = <0>; 255 polling-delay = <0>; 256 thermal-sensors = <&tsens 10>; 257 258 trips { 259 cpu-critical { 260 temperature = <105000>; 261 hysteresis = <2000>; 262 type = "critical"; 263 }; 264 265 cpu-hot { 266 temperature = <95000>; 267 hysteresis = <2000>; 268 type = "hot"; 269 }; 270 }; 271 }; 272 }; 273 274 memory { 275 device_type = "memory"; 276 reg = <0x0 0x0>; 277 }; 278 279 cpu-pmu { 280 compatible = "qcom,krait-pmu"; 281 interrupts = <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | 282 IRQ_TYPE_LEVEL_HIGH)>; 283 }; 284 285 reserved-memory { 286 #address-cells = <1>; 287 #size-cells = <1>; 288 ranges; 289 290 nss@40000000 { 291 reg = <0x40000000 0x1000000>; 292 no-map; 293 }; 294 295 smem: smem@41000000 { 296 compatible = "qcom,smem"; 297 reg = <0x41000000 0x200000>; 298 no-map; 299 300 hwlocks = <&sfpb_mutex 3>; 301 }; 302 }; 303 304 clocks { 305 cxo_board: cxo_board { 306 compatible = "fixed-clock"; 307 #clock-cells = <0>; 308 clock-frequency = <25000000>; 309 }; 310 311 pxo_board: pxo_board { 312 compatible = "fixed-clock"; 313 #clock-cells = <0>; 314 clock-frequency = <25000000>; 315 }; 316 317 sleep_clk: sleep_clk { 318 compatible = "fixed-clock"; 319 clock-frequency = <32768>; 320 #clock-cells = <0>; 321 }; 322 }; 323 324 firmware { 325 scm { 326 compatible = "qcom,scm-ipq806x", "qcom,scm"; 327 }; 328 }; 329 330 stmmac_axi_setup: stmmac-axi-config { 331 snps,wr_osr_lmt = <7>; 332 snps,rd_osr_lmt = <7>; 333 snps,blen = <16 0 0 0 0 0 0>; 334 }; 335 336 vsdcc_fixed: vsdcc-regulator { 337 compatible = "regulator-fixed"; 338 regulator-name = "SDCC Power"; 339 regulator-min-microvolt = <3300000>; 340 regulator-max-microvolt = <3300000>; 341 regulator-always-on; 342 }; 343 344 soc: soc { 345 #address-cells = <1>; 346 #size-cells = <1>; 347 ranges; 348 compatible = "simple-bus"; 349 350 rpm: rpm@108000 { 351 compatible = "qcom,rpm-ipq8064"; 352 reg = <0x00108000 0x1000>; 353 qcom,ipc = <&l2cc 0x8 2>; 354 355 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, 356 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, 357 <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 358 interrupt-names = "ack", "err", "wakeup"; 359 360 clocks = <&gcc RPM_MSG_RAM_H_CLK>; 361 clock-names = "ram"; 362 363 rpmcc: clock-controller { 364 compatible = "qcom,rpmcc-ipq806x", "qcom,rpmcc"; 365 #clock-cells = <1>; 366 }; 367 }; 368 369 ssbi@500000 { 370 compatible = "qcom,ssbi"; 371 reg = <0x00500000 0x1000>; 372 qcom,controller-type = "pmic-arbiter"; 373 }; 374 375 qfprom: efuse@700000 { 376 compatible = "qcom,ipq8064-qfprom", "qcom,qfprom"; 377 reg = <0x00700000 0x1000>; 378 #address-cells = <1>; 379 #size-cells = <1>; 380 speedbin_efuse: speedbin@c0 { 381 reg = <0xc0 0x4>; 382 }; 383 tsens_calib: calib@400 { 384 reg = <0x400 0xb>; 385 }; 386 tsens_calib_backup: calib_backup@410 { 387 reg = <0x410 0xb>; 388 }; 389 }; 390 391 qcom_pinmux: pinmux@800000 { 392 compatible = "qcom,ipq8064-pinctrl"; 393 reg = <0x00800000 0x4000>; 394 395 gpio-controller; 396 gpio-ranges = <&qcom_pinmux 0 0 69>; 397 #gpio-cells = <2>; 398 interrupt-controller; 399 #interrupt-cells = <2>; 400 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 401 402 pcie0_pins: pcie0-state { 403 pins = "gpio3"; 404 function = "pcie1_rst"; 405 drive-strength = <12>; 406 bias-disable; 407 }; 408 409 pcie1_pins: pcie1-state { 410 pins = "gpio48"; 411 function = "pcie2_rst"; 412 drive-strength = <12>; 413 bias-disable; 414 }; 415 416 pcie2_pins: pcie2-state { 417 pins = "gpio63"; 418 function = "pcie3_rst"; 419 drive-strength = <12>; 420 bias-disable; 421 }; 422 423 i2c4_pins: i2c4-state { 424 pins = "gpio12", "gpio13"; 425 function = "gsbi4"; 426 drive-strength = <12>; 427 bias-disable; 428 }; 429 430 spi_pins: spi-state { 431 pins = "gpio18", "gpio19", "gpio21"; 432 function = "gsbi5"; 433 drive-strength = <10>; 434 bias-disable; 435 }; 436 437 leds_pins: leds-state { 438 pins = "gpio7", "gpio8", "gpio9", 439 "gpio26", "gpio53"; 440 function = "gpio"; 441 drive-strength = <2>; 442 bias-pull-down; 443 output-low; 444 }; 445 446 buttons_pins: buttons-state { 447 pins = "gpio54"; 448 drive-strength = <2>; 449 bias-pull-up; 450 }; 451 452 nand_pins: nand-state { 453 nand-pins { 454 pins = "gpio34", "gpio35", "gpio36", 455 "gpio37", "gpio38", "gpio39", 456 "gpio40", "gpio41", "gpio42", 457 "gpio43", "gpio44", "gpio45", 458 "gpio46", "gpio47"; 459 function = "nand"; 460 drive-strength = <10>; 461 bias-disable; 462 }; 463 464 nand-pullup-pins { 465 pins = "gpio39"; 466 function = "nand"; 467 drive-strength = <10>; 468 bias-pull-up; 469 }; 470 471 nand-hold-pins { 472 pins = "gpio40", "gpio41", "gpio42", 473 "gpio43", "gpio44", "gpio45", 474 "gpio46", "gpio47"; 475 function = "nand"; 476 drive-strength = <10>; 477 bias-bus-hold; 478 }; 479 }; 480 481 mdio0_pins: mdio0-state { 482 pins = "gpio0", "gpio1"; 483 function = "mdio"; 484 drive-strength = <8>; 485 bias-disable; 486 }; 487 488 rgmii2_pins: rgmii2-state { 489 pins = "gpio27", "gpio28", "gpio29", 490 "gpio30", "gpio31", "gpio32", 491 "gpio51", "gpio52", "gpio59", 492 "gpio60", "gpio61", "gpio62"; 493 function = "rgmii2"; 494 drive-strength = <8>; 495 bias-disable; 496 }; 497 }; 498 499 gcc: clock-controller@900000 { 500 compatible = "qcom,gcc-ipq8064", "syscon"; 501 clocks = <&pxo_board>, <&cxo_board>, <&lcc PLL4>; 502 clock-names = "pxo", "cxo", "pll4"; 503 reg = <0x00900000 0x4000>; 504 #clock-cells = <1>; 505 #reset-cells = <1>; 506 507 tsens: thermal-sensor { 508 compatible = "qcom,ipq8064-tsens"; 509 510 nvmem-cells = <&tsens_calib>, <&tsens_calib_backup>; 511 nvmem-cell-names = "calib", "calib_backup"; 512 interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>; 513 interrupt-names = "uplow"; 514 515 #qcom,sensors = <11>; 516 #thermal-sensor-cells = <1>; 517 }; 518 }; 519 520 sfpb_mutex: hwlock@1200600 { 521 compatible = "qcom,sfpb-mutex"; 522 reg = <0x01200600 0x100>; 523 524 #hwlock-cells = <1>; 525 }; 526 527 intc: interrupt-controller@2000000 { 528 compatible = "qcom,msm-qgic2"; 529 interrupt-controller; 530 #interrupt-cells = <3>; 531 reg = <0x02000000 0x1000>, 532 <0x02002000 0x1000>; 533 }; 534 535 timer@200a000 { 536 compatible = "qcom,kpss-wdt-ipq8064", "qcom,kpss-timer", 537 "qcom,msm-timer"; 538 interrupts = <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(2) | 539 IRQ_TYPE_EDGE_RISING)>, 540 <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(2) | 541 IRQ_TYPE_EDGE_RISING)>, 542 <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(2) | 543 IRQ_TYPE_EDGE_RISING)>, 544 <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(2) | 545 IRQ_TYPE_EDGE_RISING)>, 546 <GIC_PPI 5 (GIC_CPU_MASK_SIMPLE(2) | 547 IRQ_TYPE_EDGE_RISING)>; 548 reg = <0x0200a000 0x100>; 549 clock-frequency = <25000000>; 550 clocks = <&sleep_clk>; 551 clock-names = "sleep"; 552 cpu-offset = <0x80000>; 553 }; 554 555 l2cc: clock-controller@2011000 { 556 compatible = "qcom,kpss-gcc-ipq8064", "qcom,kpss-gcc", "syscon"; 557 reg = <0x02011000 0x1000>; 558 clocks = <&gcc PLL8_VOTE>, <&pxo_board>; 559 clock-names = "pll8_vote", "pxo"; 560 #clock-cells = <0>; 561 }; 562 563 acc0: clock-controller@2088000 { 564 compatible = "qcom,kpss-acc-v1"; 565 reg = <0x02088000 0x1000>, <0x02008000 0x1000>; 566 clocks = <&gcc PLL8_VOTE>, <&pxo_board>; 567 clock-names = "pll8_vote", "pxo"; 568 clock-output-names = "acpu0_aux"; 569 #clock-cells = <0>; 570 }; 571 572 saw0: power-manager@2089000 { 573 compatible = "qcom,ipq8064-saw2-cpu", "qcom,saw2"; 574 reg = <0x02089000 0x1000>, <0x02009000 0x1000>; 575 }; 576 577 acc1: clock-controller@2098000 { 578 compatible = "qcom,kpss-acc-v1"; 579 reg = <0x02098000 0x1000>, <0x02008000 0x1000>; 580 clocks = <&gcc PLL8_VOTE>, <&pxo_board>; 581 clock-names = "pll8_vote", "pxo"; 582 clock-output-names = "acpu1_aux"; 583 #clock-cells = <0>; 584 }; 585 586 saw1: power-manager@2099000 { 587 compatible = "qcom,ipq8064-saw2-cpu", "qcom,saw2"; 588 reg = <0x02099000 0x1000>, <0x02009000 0x1000>; 589 }; 590 591 nss_common: syscon@3000000 { 592 compatible = "syscon"; 593 reg = <0x03000000 0x0000FFFF>; 594 }; 595 596 usb3_0: usb@100f8800 { 597 compatible = "qcom,ipq8064-dwc3", "qcom,dwc3"; 598 #address-cells = <1>; 599 #size-cells = <1>; 600 reg = <0x100f8800 0x8000>; 601 clocks = <&gcc USB30_0_MASTER_CLK>; 602 clock-names = "core"; 603 604 ranges; 605 606 resets = <&gcc USB30_0_MASTER_RESET>; 607 608 status = "disabled"; 609 610 dwc3_0: usb@10000000 { 611 compatible = "snps,dwc3"; 612 reg = <0x10000000 0xcd00>; 613 interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>; 614 phys = <&hs_phy_0>, <&ss_phy_0>; 615 phy-names = "usb2-phy", "usb3-phy"; 616 dr_mode = "host"; 617 snps,dis_u3_susphy_quirk; 618 }; 619 }; 620 621 hs_phy_0: phy@100f8800 { 622 compatible = "qcom,ipq806x-usb-phy-hs"; 623 reg = <0x100f8800 0x30>; 624 clocks = <&gcc USB30_0_UTMI_CLK>; 625 clock-names = "ref"; 626 #phy-cells = <0>; 627 628 status = "disabled"; 629 }; 630 631 ss_phy_0: phy@100f8830 { 632 compatible = "qcom,ipq806x-usb-phy-ss"; 633 reg = <0x100f8830 0x30>; 634 clocks = <&gcc USB30_0_MASTER_CLK>; 635 clock-names = "ref"; 636 #phy-cells = <0>; 637 638 status = "disabled"; 639 }; 640 641 usb3_1: usb@110f8800 { 642 compatible = "qcom,ipq8064-dwc3", "qcom,dwc3"; 643 #address-cells = <1>; 644 #size-cells = <1>; 645 reg = <0x110f8800 0x8000>; 646 clocks = <&gcc USB30_1_MASTER_CLK>; 647 clock-names = "core"; 648 649 ranges; 650 651 resets = <&gcc USB30_1_MASTER_RESET>; 652 653 status = "disabled"; 654 655 dwc3_1: usb@11000000 { 656 compatible = "snps,dwc3"; 657 reg = <0x11000000 0xcd00>; 658 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; 659 phys = <&hs_phy_1>, <&ss_phy_1>; 660 phy-names = "usb2-phy", "usb3-phy"; 661 dr_mode = "host"; 662 snps,dis_u3_susphy_quirk; 663 }; 664 }; 665 666 hs_phy_1: phy@110f8800 { 667 compatible = "qcom,ipq806x-usb-phy-hs"; 668 reg = <0x110f8800 0x30>; 669 clocks = <&gcc USB30_1_UTMI_CLK>; 670 clock-names = "ref"; 671 #phy-cells = <0>; 672 673 status = "disabled"; 674 }; 675 676 ss_phy_1: phy@110f8830 { 677 compatible = "qcom,ipq806x-usb-phy-ss"; 678 reg = <0x110f8830 0x30>; 679 clocks = <&gcc USB30_1_MASTER_CLK>; 680 clock-names = "ref"; 681 #phy-cells = <0>; 682 683 status = "disabled"; 684 }; 685 686 sdcc3bam: dma-controller@12182000 { 687 compatible = "qcom,bam-v1.3.0"; 688 reg = <0x12182000 0x8000>; 689 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 690 clocks = <&gcc SDC3_H_CLK>; 691 clock-names = "bam_clk"; 692 #dma-cells = <1>; 693 qcom,ee = <0>; 694 }; 695 696 sdcc1bam: dma-controller@12402000 { 697 compatible = "qcom,bam-v1.3.0"; 698 reg = <0x12402000 0x8000>; 699 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 700 clocks = <&gcc SDC1_H_CLK>; 701 clock-names = "bam_clk"; 702 #dma-cells = <1>; 703 qcom,ee = <0>; 704 }; 705 706 amba: amba { 707 compatible = "simple-bus"; 708 #address-cells = <1>; 709 #size-cells = <1>; 710 ranges; 711 712 sdcc3: mmc@12180000 { 713 compatible = "arm,pl18x", "arm,primecell"; 714 arm,primecell-periphid = <0x00051180>; 715 status = "disabled"; 716 reg = <0x12180000 0x2000>; 717 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; 718 clocks = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>; 719 clock-names = "mclk", "apb_pclk"; 720 bus-width = <8>; 721 cap-sd-highspeed; 722 cap-mmc-highspeed; 723 max-frequency = <192000000>; 724 sd-uhs-sdr104; 725 sd-uhs-ddr50; 726 vqmmc-supply = <&vsdcc_fixed>; 727 dmas = <&sdcc3bam 2>, <&sdcc3bam 1>; 728 dma-names = "tx", "rx"; 729 }; 730 731 sdcc1: mmc@12400000 { 732 status = "disabled"; 733 compatible = "arm,pl18x", "arm,primecell"; 734 arm,primecell-periphid = <0x00051180>; 735 reg = <0x12400000 0x2000>; 736 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; 737 clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>; 738 clock-names = "mclk", "apb_pclk"; 739 bus-width = <8>; 740 max-frequency = <96000000>; 741 non-removable; 742 cap-sd-highspeed; 743 cap-mmc-highspeed; 744 vmmc-supply = <&vsdcc_fixed>; 745 dmas = <&sdcc1bam 2>, <&sdcc1bam 1>; 746 dma-names = "tx", "rx"; 747 }; 748 }; 749 750 gsbi1: gsbi@12440000 { 751 compatible = "qcom,gsbi-v1.0.0"; 752 reg = <0x12440000 0x100>; 753 cell-index = <1>; 754 clocks = <&gcc GSBI1_H_CLK>; 755 clock-names = "iface"; 756 #address-cells = <1>; 757 #size-cells = <1>; 758 ranges; 759 760 syscon-tcsr = <&tcsr>; 761 762 status = "disabled"; 763 764 gsbi1_serial: serial@12450000 { 765 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; 766 reg = <0x12450000 0x100>, 767 <0x12400000 0x03>; 768 interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>; 769 clocks = <&gcc GSBI1_UART_CLK>, <&gcc GSBI1_H_CLK>; 770 clock-names = "core", "iface"; 771 772 status = "disabled"; 773 }; 774 775 gsbi1_i2c: i2c@12460000 { 776 compatible = "qcom,i2c-qup-v1.1.1"; 777 reg = <0x12460000 0x1000>; 778 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>; 779 clocks = <&gcc GSBI1_QUP_CLK>, <&gcc GSBI1_H_CLK>; 780 clock-names = "core", "iface"; 781 #address-cells = <1>; 782 #size-cells = <0>; 783 784 status = "disabled"; 785 }; 786 }; 787 788 gsbi2: gsbi@12480000 { 789 compatible = "qcom,gsbi-v1.0.0"; 790 cell-index = <2>; 791 reg = <0x12480000 0x100>; 792 clocks = <&gcc GSBI2_H_CLK>; 793 clock-names = "iface"; 794 #address-cells = <1>; 795 #size-cells = <1>; 796 ranges; 797 status = "disabled"; 798 799 syscon-tcsr = <&tcsr>; 800 801 gsbi2_serial: serial@12490000 { 802 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; 803 reg = <0x12490000 0x1000>, 804 <0x12480000 0x1000>; 805 interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>; 806 clocks = <&gcc GSBI2_UART_CLK>, <&gcc GSBI2_H_CLK>; 807 clock-names = "core", "iface"; 808 status = "disabled"; 809 }; 810 811 gsbi2_i2c: i2c@124a0000 { 812 compatible = "qcom,i2c-qup-v1.1.1"; 813 reg = <0x124a0000 0x1000>; 814 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>; 815 816 clocks = <&gcc GSBI2_QUP_CLK>, <&gcc GSBI2_H_CLK>; 817 clock-names = "core", "iface"; 818 status = "disabled"; 819 820 #address-cells = <1>; 821 #size-cells = <0>; 822 }; 823 }; 824 825 gsbi4: gsbi@16300000 { 826 compatible = "qcom,gsbi-v1.0.0"; 827 cell-index = <4>; 828 reg = <0x16300000 0x100>; 829 clocks = <&gcc GSBI4_H_CLK>; 830 clock-names = "iface"; 831 #address-cells = <1>; 832 #size-cells = <1>; 833 ranges; 834 status = "disabled"; 835 836 syscon-tcsr = <&tcsr>; 837 838 gsbi4_serial: serial@16340000 { 839 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; 840 reg = <0x16340000 0x1000>, 841 <0x16300000 0x1000>; 842 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; 843 clocks = <&gcc GSBI4_UART_CLK>, <&gcc GSBI4_H_CLK>; 844 clock-names = "core", "iface"; 845 status = "disabled"; 846 }; 847 848 i2c@16380000 { 849 compatible = "qcom,i2c-qup-v1.1.1"; 850 reg = <0x16380000 0x1000>; 851 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 852 853 clocks = <&gcc GSBI4_QUP_CLK>, <&gcc GSBI4_H_CLK>; 854 clock-names = "core", "iface"; 855 status = "disabled"; 856 857 #address-cells = <1>; 858 #size-cells = <0>; 859 }; 860 }; 861 862 gsbi6: gsbi@16500000 { 863 compatible = "qcom,gsbi-v1.0.0"; 864 reg = <0x16500000 0x100>; 865 cell-index = <6>; 866 clocks = <&gcc GSBI6_H_CLK>; 867 clock-names = "iface"; 868 #address-cells = <1>; 869 #size-cells = <1>; 870 ranges; 871 872 syscon-tcsr = <&tcsr>; 873 874 status = "disabled"; 875 876 gsbi6_i2c: i2c@16580000 { 877 compatible = "qcom,i2c-qup-v1.1.1"; 878 reg = <0x16580000 0x1000>; 879 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; 880 881 clocks = <&gcc GSBI6_QUP_CLK>, <&gcc GSBI6_H_CLK>; 882 clock-names = "core", "iface"; 883 884 #address-cells = <1>; 885 #size-cells = <0>; 886 887 status = "disabled"; 888 }; 889 890 gsbi6_spi: spi@16580000 { 891 compatible = "qcom,spi-qup-v1.1.1"; 892 reg = <0x16580000 0x1000>; 893 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; 894 895 clocks = <&gcc GSBI6_QUP_CLK>, <&gcc GSBI6_H_CLK>; 896 clock-names = "core", "iface"; 897 898 #address-cells = <1>; 899 #size-cells = <0>; 900 901 status = "disabled"; 902 }; 903 }; 904 905 gsbi7: gsbi@16600000 { 906 status = "disabled"; 907 compatible = "qcom,gsbi-v1.0.0"; 908 cell-index = <7>; 909 reg = <0x16600000 0x100>; 910 clocks = <&gcc GSBI7_H_CLK>; 911 clock-names = "iface"; 912 #address-cells = <1>; 913 #size-cells = <1>; 914 ranges; 915 syscon-tcsr = <&tcsr>; 916 917 gsbi7_serial: serial@16640000 { 918 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; 919 reg = <0x16640000 0x1000>, 920 <0x16600000 0x1000>; 921 interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; 922 clocks = <&gcc GSBI7_UART_CLK>, <&gcc GSBI7_H_CLK>; 923 clock-names = "core", "iface"; 924 status = "disabled"; 925 }; 926 927 gsbi7_i2c: i2c@16680000 { 928 compatible = "qcom,i2c-qup-v1.1.1"; 929 reg = <0x16680000 0x1000>; 930 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; 931 932 clocks = <&gcc GSBI7_QUP_CLK>, <&gcc GSBI7_H_CLK>; 933 clock-names = "core", "iface"; 934 935 #address-cells = <1>; 936 #size-cells = <0>; 937 938 status = "disabled"; 939 }; 940 }; 941 942 adm_dma: dma-controller@18300000 { 943 compatible = "qcom,adm"; 944 reg = <0x18300000 0x100000>; 945 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; 946 #dma-cells = <1>; 947 948 clocks = <&gcc ADM0_CLK>, <&gcc ADM0_PBUS_CLK>; 949 clock-names = "core", "iface"; 950 951 resets = <&gcc ADM0_RESET>, 952 <&gcc ADM0_PBUS_RESET>, 953 <&gcc ADM0_C0_RESET>, 954 <&gcc ADM0_C1_RESET>, 955 <&gcc ADM0_C2_RESET>; 956 reset-names = "clk", "pbus", "c0", "c1", "c2"; 957 qcom,ee = <0>; 958 959 status = "disabled"; 960 }; 961 962 gsbi5: gsbi@1a200000 { 963 compatible = "qcom,gsbi-v1.0.0"; 964 cell-index = <5>; 965 reg = <0x1a200000 0x100>; 966 clocks = <&gcc GSBI5_H_CLK>; 967 clock-names = "iface"; 968 #address-cells = <1>; 969 970 #size-cells = <1>; 971 ranges; 972 status = "disabled"; 973 974 syscon-tcsr = <&tcsr>; 975 976 gsbi5_serial: serial@1a240000 { 977 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; 978 reg = <0x1a240000 0x1000>, 979 <0x1a200000 0x1000>; 980 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 981 clocks = <&gcc GSBI5_UART_CLK>, <&gcc GSBI5_H_CLK>; 982 clock-names = "core", "iface"; 983 status = "disabled"; 984 }; 985 986 i2c@1a280000 { 987 compatible = "qcom,i2c-qup-v1.1.1"; 988 reg = <0x1a280000 0x1000>; 989 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 990 991 clocks = <&gcc GSBI5_QUP_CLK>, <&gcc GSBI5_H_CLK>; 992 clock-names = "core", "iface"; 993 status = "disabled"; 994 995 #address-cells = <1>; 996 #size-cells = <0>; 997 }; 998 999 spi@1a280000 { 1000 compatible = "qcom,spi-qup-v1.1.1"; 1001 reg = <0x1a280000 0x1000>; 1002 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 1003 1004 clocks = <&gcc GSBI5_QUP_CLK>, <&gcc GSBI5_H_CLK>; 1005 clock-names = "core", "iface"; 1006 status = "disabled"; 1007 1008 #address-cells = <1>; 1009 #size-cells = <0>; 1010 }; 1011 }; 1012 1013 tcsr: syscon@1a400000 { 1014 compatible = "qcom,tcsr-ipq8064", "syscon"; 1015 reg = <0x1a400000 0x100>; 1016 }; 1017 1018 rng@1a500000 { 1019 compatible = "qcom,prng"; 1020 reg = <0x1a500000 0x200>; 1021 clocks = <&gcc PRNG_CLK>; 1022 clock-names = "core"; 1023 }; 1024 1025 nand: nand-controller@1ac00000 { 1026 compatible = "qcom,ipq806x-nand"; 1027 reg = <0x1ac00000 0x800>; 1028 1029 pinctrl-0 = <&nand_pins>; 1030 pinctrl-names = "default"; 1031 1032 clocks = <&gcc EBI2_CLK>, 1033 <&gcc EBI2_AON_CLK>; 1034 clock-names = "core", "aon"; 1035 1036 dmas = <&adm_dma 3>; 1037 dma-names = "rxtx"; 1038 qcom,cmd-crci = <15>; 1039 qcom,data-crci = <3>; 1040 1041 #address-cells = <1>; 1042 #size-cells = <0>; 1043 1044 status = "disabled"; 1045 }; 1046 1047 sata_phy: sata-phy@1b400000 { 1048 compatible = "qcom,ipq806x-sata-phy"; 1049 reg = <0x1b400000 0x200>; 1050 1051 clocks = <&gcc SATA_PHY_CFG_CLK>; 1052 clock-names = "cfg"; 1053 1054 #phy-cells = <0>; 1055 status = "disabled"; 1056 }; 1057 1058 pcie0: pcie@1b500000 { 1059 compatible = "qcom,pcie-ipq8064"; 1060 reg = <0x1b500000 0x1000 1061 0x1b502000 0x80 1062 0x1b600000 0x100 1063 0x0ff00000 0x100000>; 1064 reg-names = "dbi", "elbi", "parf", "config"; 1065 device_type = "pci"; 1066 linux,pci-domain = <0>; 1067 bus-range = <0x00 0xff>; 1068 num-lanes = <1>; 1069 #address-cells = <3>; 1070 #size-cells = <2>; 1071 1072 ranges = <0x81000000 0x0 0x00000000 0x0fe00000 0x0 0x00010000 /* I/O */ 1073 0x82000000 0x0 0x08000000 0x08000000 0x0 0x07e00000>; /* MEM */ 1074 1075 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 1076 interrupt-names = "msi"; 1077 #interrupt-cells = <1>; 1078 interrupt-map-mask = <0 0 0 0x7>; 1079 interrupt-map = <0 0 0 1 &intc 0 36 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1080 <0 0 0 2 &intc 0 37 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1081 <0 0 0 3 &intc 0 38 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1082 <0 0 0 4 &intc 0 39 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1083 1084 clocks = <&gcc PCIE_A_CLK>, 1085 <&gcc PCIE_H_CLK>, 1086 <&gcc PCIE_PHY_CLK>, 1087 <&gcc PCIE_AUX_CLK>, 1088 <&gcc PCIE_ALT_REF_CLK>; 1089 clock-names = "core", "iface", "phy", "aux", "ref"; 1090 1091 assigned-clocks = <&gcc PCIE_ALT_REF_CLK>; 1092 assigned-clock-rates = <100000000>; 1093 1094 resets = <&gcc PCIE_ACLK_RESET>, 1095 <&gcc PCIE_HCLK_RESET>, 1096 <&gcc PCIE_POR_RESET>, 1097 <&gcc PCIE_PCI_RESET>, 1098 <&gcc PCIE_PHY_RESET>, 1099 <&gcc PCIE_EXT_RESET>; 1100 reset-names = "axi", "ahb", "por", "pci", "phy", "ext"; 1101 1102 pinctrl-0 = <&pcie0_pins>; 1103 pinctrl-names = "default"; 1104 1105 status = "disabled"; 1106 perst-gpios = <&qcom_pinmux 3 GPIO_ACTIVE_LOW>; 1107 1108 pcie@0 { 1109 device_type = "pci"; 1110 reg = <0x0 0x0 0x0 0x0 0x0>; 1111 bus-range = <0x01 0xff>; 1112 1113 #address-cells = <3>; 1114 #size-cells = <2>; 1115 ranges; 1116 }; 1117 }; 1118 1119 pcie1: pcie@1b700000 { 1120 compatible = "qcom,pcie-ipq8064"; 1121 reg = <0x1b700000 0x1000 1122 0x1b702000 0x80 1123 0x1b800000 0x100 1124 0x31f00000 0x100000>; 1125 reg-names = "dbi", "elbi", "parf", "config"; 1126 device_type = "pci"; 1127 linux,pci-domain = <1>; 1128 bus-range = <0x00 0xff>; 1129 num-lanes = <1>; 1130 #address-cells = <3>; 1131 #size-cells = <2>; 1132 1133 ranges = <0x81000000 0x0 0x00000000 0x31e00000 0x0 0x00010000 /* I/O */ 1134 0x82000000 0x0 0x2e000000 0x2e000000 0x0 0x03e00000>; /* MEM */ 1135 1136 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; 1137 interrupt-names = "msi"; 1138 #interrupt-cells = <1>; 1139 interrupt-map-mask = <0 0 0 0x7>; 1140 interrupt-map = <0 0 0 1 &intc 0 58 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1141 <0 0 0 2 &intc 0 59 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1142 <0 0 0 3 &intc 0 60 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1143 <0 0 0 4 &intc 0 61 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1144 1145 clocks = <&gcc PCIE_1_A_CLK>, 1146 <&gcc PCIE_1_H_CLK>, 1147 <&gcc PCIE_1_PHY_CLK>, 1148 <&gcc PCIE_1_AUX_CLK>, 1149 <&gcc PCIE_1_ALT_REF_CLK>; 1150 clock-names = "core", "iface", "phy", "aux", "ref"; 1151 1152 assigned-clocks = <&gcc PCIE_1_ALT_REF_CLK>; 1153 assigned-clock-rates = <100000000>; 1154 1155 resets = <&gcc PCIE_1_ACLK_RESET>, 1156 <&gcc PCIE_1_HCLK_RESET>, 1157 <&gcc PCIE_1_POR_RESET>, 1158 <&gcc PCIE_1_PCI_RESET>, 1159 <&gcc PCIE_1_PHY_RESET>, 1160 <&gcc PCIE_1_EXT_RESET>; 1161 reset-names = "axi", "ahb", "por", "pci", "phy", "ext"; 1162 1163 pinctrl-0 = <&pcie1_pins>; 1164 pinctrl-names = "default"; 1165 1166 status = "disabled"; 1167 perst-gpios = <&qcom_pinmux 48 GPIO_ACTIVE_LOW>; 1168 1169 pcie@0 { 1170 device_type = "pci"; 1171 reg = <0x0 0x0 0x0 0x0 0x0>; 1172 bus-range = <0x01 0xff>; 1173 1174 #address-cells = <3>; 1175 #size-cells = <2>; 1176 ranges; 1177 }; 1178 }; 1179 1180 pcie2: pcie@1b900000 { 1181 compatible = "qcom,pcie-ipq8064"; 1182 reg = <0x1b900000 0x1000 1183 0x1b902000 0x80 1184 0x1ba00000 0x100 1185 0x35f00000 0x100000>; 1186 reg-names = "dbi", "elbi", "parf", "config"; 1187 device_type = "pci"; 1188 linux,pci-domain = <2>; 1189 bus-range = <0x00 0xff>; 1190 num-lanes = <1>; 1191 #address-cells = <3>; 1192 #size-cells = <2>; 1193 1194 ranges = <0x81000000 0x0 0x00000000 0x35e00000 0x0 0x00010000 /* I/O */ 1195 0x82000000 0x0 0x32000000 0x32000000 0x0 0x03e00000>; /* MEM */ 1196 1197 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 1198 interrupt-names = "msi"; 1199 #interrupt-cells = <1>; 1200 interrupt-map-mask = <0 0 0 0x7>; 1201 interrupt-map = <0 0 0 1 &intc 0 72 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1202 <0 0 0 2 &intc 0 73 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1203 <0 0 0 3 &intc 0 74 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1204 <0 0 0 4 &intc 0 75 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1205 1206 clocks = <&gcc PCIE_2_A_CLK>, 1207 <&gcc PCIE_2_H_CLK>, 1208 <&gcc PCIE_2_PHY_CLK>, 1209 <&gcc PCIE_2_AUX_CLK>, 1210 <&gcc PCIE_2_ALT_REF_CLK>; 1211 clock-names = "core", "iface", "phy", "aux", "ref"; 1212 1213 assigned-clocks = <&gcc PCIE_2_ALT_REF_CLK>; 1214 assigned-clock-rates = <100000000>; 1215 1216 resets = <&gcc PCIE_2_ACLK_RESET>, 1217 <&gcc PCIE_2_HCLK_RESET>, 1218 <&gcc PCIE_2_POR_RESET>, 1219 <&gcc PCIE_2_PCI_RESET>, 1220 <&gcc PCIE_2_PHY_RESET>, 1221 <&gcc PCIE_2_EXT_RESET>; 1222 reset-names = "axi", "ahb", "por", "pci", "phy", "ext"; 1223 1224 pinctrl-0 = <&pcie2_pins>; 1225 pinctrl-names = "default"; 1226 1227 status = "disabled"; 1228 perst-gpios = <&qcom_pinmux 63 GPIO_ACTIVE_LOW>; 1229 1230 pcie@0 { 1231 device_type = "pci"; 1232 reg = <0x0 0x0 0x0 0x0 0x0>; 1233 bus-range = <0x01 0xff>; 1234 1235 #address-cells = <3>; 1236 #size-cells = <2>; 1237 ranges; 1238 }; 1239 }; 1240 1241 qsgmii_csr: syscon@1bb00000 { 1242 compatible = "syscon"; 1243 reg = <0x1bb00000 0x000001FF>; 1244 }; 1245 1246 lcc: clock-controller@28000000 { 1247 compatible = "qcom,lcc-ipq8064"; 1248 reg = <0x28000000 0x1000>; 1249 #clock-cells = <1>; 1250 #reset-cells = <1>; 1251 }; 1252 1253 lpass@28100000 { 1254 compatible = "qcom,lpass-cpu"; 1255 status = "disabled"; 1256 clocks = <&lcc AHBIX_CLK>, 1257 <&lcc MI2S_OSR_CLK>, 1258 <&lcc MI2S_BIT_CLK>; 1259 clock-names = "ahbix-clk", 1260 "mi2s-osr-clk", 1261 "mi2s-bit-clk"; 1262 interrupts = <GIC_SPI 85 IRQ_TYPE_EDGE_RISING>; 1263 interrupt-names = "lpass-irq-lpaif"; 1264 reg = <0x28100000 0x10000>; 1265 reg-names = "lpass-lpaif"; 1266 }; 1267 1268 sata: sata@29000000 { 1269 compatible = "qcom,ipq806x-ahci", "generic-ahci"; 1270 reg = <0x29000000 0x180>; 1271 1272 interrupts = <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>; 1273 1274 clocks = <&gcc SFAB_SATA_S_H_CLK>, 1275 <&gcc SATA_H_CLK>, 1276 <&gcc SATA_A_CLK>, 1277 <&gcc SATA_RXOOB_CLK>, 1278 <&gcc SATA_PMALIVE_CLK>; 1279 clock-names = "slave_iface", "iface", "core", 1280 "rxoob", "pmalive"; 1281 1282 assigned-clocks = <&gcc SATA_RXOOB_CLK>, <&gcc SATA_PMALIVE_CLK>; 1283 assigned-clock-rates = <100000000>, <100000000>; 1284 1285 phys = <&sata_phy>; 1286 phy-names = "sata-phy"; 1287 status = "disabled"; 1288 }; 1289 1290 gmac0: ethernet@37000000 { 1291 device_type = "network"; 1292 compatible = "qcom,ipq806x-gmac", "snps,dwmac"; 1293 reg = <0x37000000 0x200000>; 1294 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>; 1295 interrupt-names = "macirq"; 1296 1297 snps,axi-config = <&stmmac_axi_setup>; 1298 snps,pbl = <32>; 1299 snps,aal; 1300 1301 qcom,nss-common = <&nss_common>; 1302 qcom,qsgmii-csr = <&qsgmii_csr>; 1303 1304 clocks = <&gcc GMAC_CORE1_CLK>; 1305 clock-names = "stmmaceth"; 1306 1307 resets = <&gcc GMAC_CORE1_RESET>, 1308 <&gcc GMAC_AHB_RESET>; 1309 reset-names = "stmmaceth", "ahb"; 1310 1311 status = "disabled"; 1312 }; 1313 1314 gmac1: ethernet@37200000 { 1315 device_type = "network"; 1316 compatible = "qcom,ipq806x-gmac", "snps,dwmac"; 1317 reg = <0x37200000 0x200000>; 1318 interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 1319 interrupt-names = "macirq"; 1320 1321 snps,axi-config = <&stmmac_axi_setup>; 1322 snps,pbl = <32>; 1323 snps,aal; 1324 1325 qcom,nss-common = <&nss_common>; 1326 qcom,qsgmii-csr = <&qsgmii_csr>; 1327 1328 clocks = <&gcc GMAC_CORE2_CLK>; 1329 clock-names = "stmmaceth"; 1330 1331 resets = <&gcc GMAC_CORE2_RESET>, 1332 <&gcc GMAC_AHB_RESET>; 1333 reset-names = "stmmaceth", "ahb"; 1334 1335 status = "disabled"; 1336 }; 1337 1338 gmac2: ethernet@37400000 { 1339 device_type = "network"; 1340 compatible = "qcom,ipq806x-gmac", "snps,dwmac"; 1341 reg = <0x37400000 0x200000>; 1342 interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>; 1343 interrupt-names = "macirq"; 1344 1345 snps,axi-config = <&stmmac_axi_setup>; 1346 snps,pbl = <32>; 1347 snps,aal; 1348 1349 qcom,nss-common = <&nss_common>; 1350 qcom,qsgmii-csr = <&qsgmii_csr>; 1351 1352 clocks = <&gcc GMAC_CORE3_CLK>; 1353 clock-names = "stmmaceth"; 1354 1355 resets = <&gcc GMAC_CORE3_RESET>, 1356 <&gcc GMAC_AHB_RESET>; 1357 reset-names = "stmmaceth", "ahb"; 1358 1359 status = "disabled"; 1360 }; 1361 1362 gmac3: ethernet@37600000 { 1363 device_type = "network"; 1364 compatible = "qcom,ipq806x-gmac", "snps,dwmac"; 1365 reg = <0x37600000 0x200000>; 1366 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; 1367 interrupt-names = "macirq"; 1368 1369 snps,axi-config = <&stmmac_axi_setup>; 1370 snps,pbl = <32>; 1371 snps,aal; 1372 1373 qcom,nss-common = <&nss_common>; 1374 qcom,qsgmii-csr = <&qsgmii_csr>; 1375 1376 clocks = <&gcc GMAC_CORE4_CLK>; 1377 clock-names = "stmmaceth"; 1378 1379 resets = <&gcc GMAC_CORE4_RESET>, 1380 <&gcc GMAC_AHB_RESET>; 1381 reset-names = "stmmaceth", "ahb"; 1382 1383 status = "disabled"; 1384 }; 1385 }; 1386}; 1387