Lines Matching +full:axi +full:- +full:pcie +full:- +full:host +full:- +full:1
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/microchip,pcie-host.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Microchip PCIe Root Port Bridge Controller
10 - Daire McNamara <daire.mcnamara@microchip.com>
13 - $ref: plda,xpressrich3-axi-common.yaml#
14 - $ref: /schemas/interrupt-controller/msi-controller.yaml#
18 const: microchip,pcie-host-1.0 # PolarFire
30 minItems: 1
32 - description: FIC0's clock
33 - description: FIC1's clock
34 - description: FIC2's clock
35 - description: FIC3's clock
37 clock-names:
41 0-3
42 minItems: 1
45 pattern: '^fic[0-3]$'
48 minItems: 1
51 dma-ranges:
52 minItems: 1
58 - |
60 #address-cells = <2>;
61 #size-cells = <2>;
62 pcie0: pcie@2030000000 {
63 compatible = "microchip,pcie-host-1.0";
66 reg-names = "cfg", "apb";
68 #address-cells = <3>;
69 #size-cells = <2>;
70 #interrupt-cells = <1>;
72 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
73 interrupt-map = <0 0 0 1 &pcie_intc0 0>,
74 <0 0 0 2 &pcie_intc0 1>,
77 interrupt-parent = <&plic0>;
78 msi-parent = <&pcie0>;
79 msi-controller;
80 bus-range = <0x00 0x7f>;
82 pcie_intc0: interrupt-controller {
83 #address-cells = <0>;
84 #interrupt-cells = <1>;
85 interrupt-controller;