1 // SPDX-License-Identifier: GPL-2.0
3  * Microchip AXI PCIe Bridge host controller driver
5  * Copyright (c) 2018 - 2020 Microchip Corporation. All rights reserved.
18 #include <linux/pci-ecam.h>
22 #include "pcie-plda.h"
24 /* PCIe Bridge Phy and Controller Phy offsets */
31 /* PCIe Controller Phy Regs */
52 #define  ECC_CONTROL_TX_RAM_INJ_ERROR_1		BIT(1)
73 #define  PCIE_EVENT_INT_HOTRST_EXIT_INT		BIT(1)
83 /* PCIe Config space MSI capability structure */
88 #define EVENT_PCIE_HOTRST_EXIT			1
134 	.mask_high = 1, \
143 	.mask_high = 1, \
150 	.mask_high = 1, \
203 	LOCAL_EVENT_CAUSE(DMA_ERROR_ENGINE_1, "dma engine 1 error"),
204 	LOCAL_EVENT_CAUSE(A_ATR_EVT_POST_ERR, "axi write request error"),
205 	LOCAL_EVENT_CAUSE(A_ATR_EVT_FETCH_ERR, "axi read request error"),
206 	LOCAL_EVENT_CAUSE(A_ATR_EVT_DISCARD_ERR, "axi read timeout"),
207 	LOCAL_EVENT_CAUSE(P_ATR_EVT_POST_ERR, "pcie write request error"),
208 	LOCAL_EVENT_CAUSE(P_ATR_EVT_FETCH_ERR, "pcie read request error"),
209 	LOCAL_EVENT_CAUSE(P_ATR_EVT_DISCARD_ERR, "pcie read timeout"),
300 	struct plda_msi *msi = &port->plda.msi;  in mc_pcie_enable_msi()
315 	writel_relaxed(lower_32_bits(msi->vector_phy),  in mc_pcie_enable_msi()
317 	writel_relaxed(upper_32_bits(msi->vector_phy),  in mc_pcie_enable_msi()
328 	void __iomem *ctrl_base_addr = port->axi_base_addr + MC_PCIE_CTRL_ADDR;  in pcie_events()
341 	void __iomem *ctrl_base_addr = port->axi_base_addr + MC_PCIE_CTRL_ADDR;  in sec_errors()
354 	void __iomem *ctrl_base_addr = port->axi_base_addr + MC_PCIE_CTRL_ADDR;  in ded_errors()
367 	void __iomem *bridge_base_addr = port->axi_base_addr + MC_PCIE_BRIDGE_ADDR;  in local_events()
394 	struct device *dev = port->dev;  in mc_event_handler()
397 	data = irq_domain_get_irq_data(port->event_domain, irq);  in mc_event_handler()
399 	if (event_cause[data->hwirq].str)  in mc_event_handler()
400 		dev_err_ratelimited(dev, "%s\n", event_cause[data->hwirq].str);  in mc_event_handler()
402 		dev_err_ratelimited(dev, "bad event IRQ %ld\n", data->hwirq);  in mc_event_handler()
411 	u32 event = data->hwirq;  in mc_ack_event_irq()
415 	addr = mc_port->axi_base_addr + event_descs[event].base +  in mc_ack_event_irq()
427 	u32 event = data->hwirq;  in mc_mask_event_irq()
432 	addr = mc_port->axi_base_addr + event_descs[event].base +  in mc_mask_event_irq()
443 	raw_spin_lock(&port->lock);  in mc_mask_event_irq()
451 	raw_spin_unlock(&port->lock);  in mc_mask_event_irq()
458 	u32 event = data->hwirq;  in mc_unmask_event_irq()
463 	addr = mc_port->axi_base_addr + event_descs[event].base +  in mc_unmask_event_irq()
476 	raw_spin_lock(&port->lock);  in mc_unmask_event_irq()
483 	raw_spin_unlock(&port->lock);  in mc_unmask_event_irq()
487 	.name = "Microchip PCIe EVENT",
526 	 * PCIe may be clocked via Fabric Interface using between 1 and 4  in mc_pcie_init_clks()
541 	return devm_request_irq(plda->dev, event_irq, mc_event_handler,  in mc_request_event_irq()
557 	void __iomem *ctrl_base_addr = port->axi_base_addr + MC_PCIE_CTRL_ADDR;  in mc_clear_secs()
566 	void __iomem *ctrl_base_addr = port->axi_base_addr + MC_PCIE_CTRL_ADDR;  in mc_clear_deds()
575 	void __iomem *bridge_base_addr = port->axi_base_addr + MC_PCIE_BRIDGE_ADDR;  in mc_disable_interrupts()
576 	void __iomem *ctrl_base_addr = port->axi_base_addr + MC_PCIE_CTRL_ADDR;  in mc_disable_interrupts()
601 	/* Disable PCIe events and clear any outstanding */  in mc_disable_interrupts()
610 	/* Disable host interrupts and clear any outstanding */  in mc_disable_interrupts()
617 	struct device *dev = cfg->parent;  in mc_platform_init()
621 		port->axi_base_addr + MC_PCIE_BRIDGE_ADDR;  in mc_platform_init()
624 	/* Configure address translation table 0 for PCIe config space */  in mc_platform_init()
625 	plda_pcie_setup_window(bridge_base_addr, 0, cfg->res.start,  in mc_platform_init()
626 			       cfg->res.start,  in mc_platform_init()
627 			       resource_size(&cfg->res));  in mc_platform_init()
630 	mc_pcie_enable_msi(port, cfg->win);  in mc_platform_init()
632 	/* Configure non-config space outbound ranges */  in mc_platform_init()
633 	ret = plda_pcie_setup_iomems(bridge, &port->plda);  in mc_platform_init()
637 	port->plda.event_ops = &mc_event_ops;  in mc_platform_init()
638 	port->plda.event_irq_chip = &mc_event_irq_chip;  in mc_platform_init()
639 	port->plda.events_bitmap = GENMASK(NUM_EVENTS - 1, 0);  in mc_platform_init()
642 	ret = plda_init_interrupts(pdev, &port->plda, &mc_event);  in mc_platform_init()
651 	struct device *dev = &pdev->dev;  in mc_host_probe()
659 		return -ENOMEM;  in mc_host_probe()
661 	plda = &port->plda;  in mc_host_probe()
662 	plda->dev = dev;  in mc_host_probe()
664 	port->axi_base_addr = devm_platform_ioremap_resource(pdev, 1);  in mc_host_probe()
665 	if (IS_ERR(port->axi_base_addr))  in mc_host_probe()
666 		return PTR_ERR(port->axi_base_addr);  in mc_host_probe()
670 	bridge_base_addr = port->axi_base_addr + MC_PCIE_BRIDGE_ADDR;  in mc_host_probe()
671 	plda->bridge_addr = bridge_base_addr;  in mc_host_probe()
672 	plda->num_events = NUM_EVENTS;  in mc_host_probe()
674 	/* Allow enabling MSI by disabling MSI-X */  in mc_host_probe()
684 	plda->msi.num_vectors = 1 << val;  in mc_host_probe()
687 	plda->msi.vector_phy = readl_relaxed(bridge_base_addr + IMSI_ADDR);  in mc_host_probe()
692 		return -ENODEV;  in mc_host_probe()
709 		.compatible = "microchip,pcie-host-1.0",
720 		.name = "microchip-pcie",
728 MODULE_DESCRIPTION("Microchip PCIe host controller driver");