Searched +full:mdio +full:- +full:connected (Results 1 – 25 of 181) sorted by relevance
12345678
| /linux-6.12.1/Documentation/devicetree/bindings/net/ |
| D | ibm,emac.txt | 8 correct clock-frequency property.
13 - device_type : "network"
15 - compatible : compatible list, contains 2 entries, first is
16 "ibm,emac-CHIP" where CHIP is the host ASIC (440gx,
18 "ibm,emac4". For Axon, thus, we have: "ibm,emac-axon",
20 - interrupts : <interrupt mapping for EMAC IRQ and WOL IRQ>
21 - reg : <registers mapping>
22 - local-mac-address : 6 bytes, MAC address
23 - mal-device : phandle of the associated McMAL node
24 - mal-tx-channel : 1 cell, index of the tx channel on McMAL associated
[all …]
|
| D | mdio-mux.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/net/mdio-mux.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Common MDIO bus multiplexer/switch properties.
10 - Andrew Lunn <andrew@lunn.ch>
13 An MDIO bus multiplexer/switch will have several child busses that are
14 numbered uniquely in a device dependent manner. The nodes for an MDIO
18 mdio-parent-bus:
21 The phandle of the MDIO bus that this multiplexer's master-side port is
[all …]
|
| D | qcom,ipq8064-mdio.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/net/qcom,ipq8064-mdio.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm ipq806x MDIO bus controller
10 - Ansuel Smith <ansuelsmth@gmail.com>
13 The ipq806x soc have a MDIO dedicated controller that is
14 used to communicate with the gmac phy connected.
17 - $ref: mdio.yaml#
21 const: qcom,ipq8064-mdio
[all …]
|
| D | mdio-mux-mmioreg.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/net/mdio-mux-mmioreg.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Properties for an MDIO bus multiplexer controlled by a memory-mapped device
10 - Andrew Lunn <andrew@lunn.ch>
13 This is a special case of a MDIO bus multiplexer. A memory-mapped device,
14 like an FPGA, is used to control which child bus is connected. The mdio-mux
15 node must be a child of the memory-mapped device. The driver currently only
16 supports devices with 8, 16 or 32-bit registers.
[all …]
|
| D | mediatek,star-emac.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/mediatek,star-emac.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Bartosz Golaszewski <bgolaszewski@baylibre.com>
14 It's compliant with 802.3 standards and supports half- and full-duplex
15 modes with flow-control as well as CRC offloading and VLAN tags.
18 - $ref: ethernet-controller.yaml#
23 - mediatek,mt8516-eth
24 - mediatek,mt8518-eth
[all …]
|
| D | fsl,fman-mdio.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/fsl,fman-mdio.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Freescale Frame Manager MDIO Device
10 - Frank Li <Frank.Li@nxp.com>
12 description: FMan MDIO Node.
13 The MDIO is a bus to which the PHY devices are connected.
18 - fsl,fman-mdio
19 - fsl,fman-xmdio
[all …]
|
| D | marvell,mvusb.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Marvell USB to MDIO Controller
10 - Tobias Waldekranz <tobias@waldekranz.com>
15 using the standard MDIO interface.
17 Since the device is connected over USB, there is no strict requirement of
23 - $ref: mdio.yaml#
33 - compatible
34 - reg
[all …]
|
| D | fsl-tsec-phy.txt | 1 * MDIO IO device
3 The MDIO is a bus to which the PHY devices are connected. For each
5 the definition of the PHY node in booting-without-of.txt for an example
9 - reg : Offset and length of the register set for the device, and optionally
14 - compatible : Should define the compatible device type for the
15 mdio. Currently supported strings/devices are:
16 - "fsl,gianfar-tbi"
17 - "fsl,gianfar-mdio"
18 - "fsl,etsec2-tbi"
19 - "fsl,etsec2-mdio"
[all …]
|
| D | xlnx,axi-ethernet.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/xlnx,axi-ethernet.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
22 - Radhey Shyam Pandey <radhey.shyam.pandey@xilinx.com>
27 - xlnx,axi-ethernet-1.00.a
28 - xlnx,axi-ethernet-1.01.a
29 - xlnx,axi-ethernet-2.01.a
35 axistream-connected is specified, in which case the reg
42 - description: Ethernet core interrupt
[all …]
|
| D | hisilicon-hip04-net.txt | 6 - compatible: should be "hisilicon,hip04-mac".
7 - reg: address and length of the register set for the device.
8 - interrupts: interrupt for the device.
9 - port-handle: <phandle port channel>
11 port, port number connected to the controller
14 - phy-mode: see ethernet.txt [1].
17 - phy-handle: see ethernet.txt [1].
22 * MDIO bus node:
26 - compatible: should be "hisilicon,mdio".
27 - Inherits from MDIO bus node binding [2]
[all …]
|
| D | xlnx,gmii-to-rgmii.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/xlnx,gmii-to-rgmii.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Harini Katakam <harini.katakam@amd.com>
14 Independent Interface (RGMII) core provides the RGMII between RGMII-compliant
17 The Management Data Input/Output (MDIO) interface is used to configure the
19 different speed modes by configuring the converter register through mdio write.
20 The core cannot function without an external phy connected to it.
24 const: xlnx,gmii-to-rgmii-1.0
[all …]
|
| D | mdio-mux-gpio.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/net/mdio-mux-gpio.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Properties for an MDIO bus multiplexer/switch controlled by GPIO pins.
10 - Andrew Lunn <andrew@lunn.ch>
13 This is a special case of a MDIO bus multiplexer. One or more GPIO
14 lines are used to control which child bus is connected.
17 - $ref: /schemas/net/mdio-mux.yaml#
21 const: mdio-mux-gpio
[all …]
|
| /linux-6.12.1/drivers/net/dsa/realtek/ |
| D | realtek-mdio.c | 1 // SPDX-License-Identifier: GPL-2.0+
2 /* Realtek MDIO interface driver
6 * RTL8366 - The original version, apparently
7 * RTL8369 - Similar enough to have the same datsheet as RTL8366
8 * RTL8366RB - Probably reads out "RTL8366 revision B", has a quite
10 * RTL8366S - Is this "RTL8366 super"?
11 * RTL8367 - Has an OpenWRT driver as well
12 * RTL8368S - Seems to be an alternative name for RTL8366RB
13 * RTL8370 - Also uses SMI
19 * Copyright (C) 2009-2010 Gabor Juhos <juhosg@openwrt.org>
[all …]
|
| D | realtek-smi.c | 1 // SPDX-License-Identifier: GPL-2.0+
5 * The SMI protocol piggy-backs the MDIO MDC and MDIO signals levels
6 * but the protocol is not MDIO at all. Instead it is a Realtek
7 * pecularity that need to bit-bang the lines in a special way to
12 * RTL8366 - The original version, apparently
13 * RTL8369 - Similar enough to have the same datsheet as RTL8366
14 * RTL8366RB - Probably reads out "RTL8366 revision B", has a quite
16 * RTL8366S - Is this "RTL8366 super"?
17 * RTL8367 - Has an OpenWRT driver as well
18 * RTL8368S - Seems to be an alternative name for RTL8366RB
[all …]
|
| /linux-6.12.1/drivers/net/dsa/b53/ |
| D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
15 tristate "B53 SPI connected switch driver"
21 tristate "B53 MDIO connected switch driver"
24 Select to enable support for registering switches configured through MDIO.
27 tristate "B53 MMAP connected switch driver"
31 Select to enable support for memory-mapped switches like the BCM63XX
35 tristate "B53 SRAB connected switch driver"
40 Select to enable support for memory-mapped Switch Register Access
|
| /linux-6.12.1/Documentation/devicetree/bindings/net/dsa/ |
| D | qca8k.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - John Crispin <john@phrozen.org>
13 If the QCA8K switch is connect to an SoC's external mdio-bus, each subnode
15 it is connected to. This is because there is no N:N mapping of port and PHY
16 ID. To declare the internal mdio-bus configuration, declare an MDIO node in
18 PHY it is connected to. In this config, an internal mdio-bus is registered and
19 the MDIO master is used for communication. Mixed external and internal
20 mdio-bus configurations are not supported by the hardware.
[all …]
|
| D | marvell,mv88e6xxx.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Andrew Lunn <andrew@lunn.ch>
22 - enum:
23 - marvell,mv88e6085
24 - marvell,mv88e6190
25 - marvell,mv88e6250
43 - items:
44 - const: marvell,turris-mox-mv88e6085
[all …]
|
| D | marvell,mv88e6060.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Andrew Lunn <andrew@lunn.ch>
15 MDIO address of the switch to be 0x10 or 0x00, and on the MDIO bus
16 connected to the switch, the PHYs inside the switch appear as
17 independent devices on address 0x00-0x04 or 0x10-0x14, so in difference
19 MDIO bus for the PHY devices.
31 reset-gpios:
37 - $ref: dsa.yaml#/$defs/ethernet-ports
[all …]
|
| D | mediatek,mt7530.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Arınç ÜNAL <arinc.unal@arinc9.com>
11 - Landen Chao <Landen.Chao@mediatek.com>
12 - DENG Qingfang <dqfext@gmail.com>
13 - Sean Wang <sean.wang@mediatek.com>
14 - Daniel Golle <daniel@makrotopia.org>
17 There are three versions of MT7530, standalone, in a multi-chip module and
18 built-into a SoC.
[all …]
|
| /linux-6.12.1/Documentation/devicetree/bindings/net/pcs/ |
| D | snps,dw-xpcs.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/pcs/snps,dw-xpcs.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Serge Semin <fancer.lancer@gmail.com>
17 optionally synthesized with a vendor-specific interface connected to
21 The PCS CSRs can be accessible either over the Ethernet MDIO bus or directly
28 - description: Synopsys DesignWare XPCS with none or unknown PMA
29 const: snps,dw-xpcs
30 - description: Synopsys DesignWare XPCS with Consumer Gen1 3G PMA
[all …]
|
| /linux-6.12.1/drivers/net/dsa/ |
| D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
20 tristate "DSA mock-up Ethernet switch chip support"
24 This enables support for a fake mock-up switch chip which
44 switch chips. Multi-chip module MT7530 in MT7621AT, MT7621DAT,
45 MT7621ST and MT7623AI SoCs, and built-in switch in MT7988 SoC are
49 tristate "MediaTek MT7530 MDIO interface driver"
55 chips which are connected via MDIO, as well as multi-chip
65 This enables support for the built-in Ethernet switch found
69 accessible via MDIO.
111 tristate "SMSC/Microchip LAN9303 3-ports 10/100 ethernet switch in I2C managed mode"
[all …]
|
| /linux-6.12.1/Documentation/firmware-guide/acpi/dsd/ |
| D | phy.rst | 1 .. SPDX-License-Identifier: GPL-2.0
4 MDIO bus and PHYs in ACPI
7 The PHYs on an MDIO bus [phy] are probed and registered using
11 on the MDIO bus have to be referenced.
14 for connecting PHYs on the MDIO bus [dsd-properties-rules] to the MAC layer.
17 Properties UUID For _DSD" [dsd-guide] document and the
18 daffd814-6eba-4d8c-8a91-bc9bbf4aa301 UUID must be used in the Device
21 phy-handle
22 ----------
23 For each MAC node, a device property "phy-handle" is used to reference
[all …]
|
| /linux-6.12.1/Documentation/networking/dsa/ |
| D | bcm_sf2.rst | 8 - xDSL gateways such as BCM63138
9 - streaming/multimedia Set Top Box such as BCM7445
10 - Cable Modem/residential gateways such as BCM7145/BCM3390
13 ports, offering a range of built-in and customizable interfaces:
15 - single integrated Gigabit PHY
16 - quad integrated Gigabit PHY
17 - quad external Gigabit PHY w/ MDIO multiplexer
18 - integrated MoCA PHY
19 - several external MII/RevMII/GMII/RGMII interfaces
22 fail-over not to lose packets during a MoCA role re-election, as well as out of
[all …]
|
| D | dsa.rst | 22 An Ethernet switch typically comprises multiple front-panel ports and one
24 presence of a management port connected to an Ethernet controller capable of
27 gateways, or even top-of-rack switches. This host Ethernet controller will
34 of multiple switches connected to each other is called a "switch tree".
36 For each front-panel port, DSA creates specialized network devices which are
37 used as controlling and data-flowing endpoints for use by the Linux networking
46 - what port is this frame coming from
47 - what was the reason why this frame got forwarded
48 - how to send CPU originated traffic to specific ports
52 on Port-based VLAN IDs).
[all …]
|
| /linux-6.12.1/drivers/net/ethernet/freescale/ |
| D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
35 Say Y here if you want to use the built-in 10/100 Fast ethernet
45 This option enables support for the MPC5200's on-chip
50 bool "FEC MPC52xx MDIO bus driver"
55 an external MII PHY chip or 10 Mbps 7-wire interface
57 If your board uses an external PHY connected to FEC, enable this.
65 tristate "Freescale PQ MDIO"
68 This driver supports the MDIO bus used by the gianfar and UCC drivers.
71 tristate "Freescale XGMAC MDIO"
77 This driver supports the MDIO bus on the Fman 10G Ethernet MACs, and
|
12345678