| /linux-6.12.1/drivers/clk/baikal-t1/ |
| D | ccu-div.c | 12 #define pr_fmt(fmt) "bt1-ccu-div: " fmt
27 #include "ccu-div.h"
61 unsigned long div) in ccu_div_lock_delay_ns() argument
63 u64 ns = 4ULL * (div ?: 1) * NSEC_PER_SEC; in ccu_div_lock_delay_ns()
71 unsigned long div) in ccu_div_calc_freq() argument
73 return ref_clk / (div ?: 1); in ccu_div_calc_freq()
76 static int ccu_div_var_update_clkdiv(struct ccu_div *div, in ccu_div_var_update_clkdiv() argument
87 if (div->features & CCU_DIV_LOCK_SHIFTED) in ccu_div_var_update_clkdiv()
92 regmap_update_bits(div->sys_regs, div->reg_ctl, in ccu_div_var_update_clkdiv()
102 regmap_read(div->sys_regs, div->reg_ctl, &val); in ccu_div_var_update_clkdiv()
[all …]
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| /linux-6.12.1/drivers/clk/berlin/ |
| D | berlin2-div.c | 16 #include "berlin2-div.h"
36 * (D) constant div-by-3 clock divider
38 * (F) constant div-by-3 clock mux controlled by <D3Switch>
46 * Also, clock gate and pll mux is not available on every div cell, so
67 struct berlin2_div *div = to_berlin2_div(hw); in berlin2_div_is_enabled() local
68 struct berlin2_div_map *map = &div->map; in berlin2_div_is_enabled()
71 if (div->lock) in berlin2_div_is_enabled()
72 spin_lock(div->lock); in berlin2_div_is_enabled()
74 reg = readl_relaxed(div->base + map->gate_offs); in berlin2_div_is_enabled()
77 if (div->lock) in berlin2_div_is_enabled()
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| /linux-6.12.1/drivers/clk/imx/ |
| D | clk-divider-gate.c | 21 struct clk_divider *div = to_clk_divider(hw); in to_clk_divider_gate() local
23 return container_of(div, struct clk_divider_gate, divider); in to_clk_divider_gate()
29 struct clk_divider *div = to_clk_divider(hw); in clk_divider_gate_recalc_rate_ro() local
32 val = readl(div->reg) >> div->shift; in clk_divider_gate_recalc_rate_ro()
33 val &= clk_div_mask(div->width); in clk_divider_gate_recalc_rate_ro()
37 return divider_recalc_rate(hw, parent_rate, val, div->table, in clk_divider_gate_recalc_rate_ro()
38 div->flags, div->width); in clk_divider_gate_recalc_rate_ro()
45 struct clk_divider *div = to_clk_divider(hw); in clk_divider_gate_recalc_rate() local
49 spin_lock_irqsave(div->lock, flags); in clk_divider_gate_recalc_rate()
54 val = readl(div->reg) >> div->shift; in clk_divider_gate_recalc_rate()
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| /linux-6.12.1/drivers/clk/ti/ |
| D | divider.c | 26 for (clkt = table; clkt->div; clkt++) in _get_table_div()
28 return clkt->div; in _get_table_div()
41 for (clkt = divider->table; clkt->div; clkt++) in _setup_mask()
72 unsigned int div) in _get_table_val() argument
76 for (clkt = table; clkt->div; clkt++) in _get_table_val()
77 if (clkt->div == div) in _get_table_val()
82 static unsigned int _get_val(struct clk_omap_divider *divider, u8 div) in _get_val() argument
85 return div; in _get_val()
87 return __ffs(div); in _get_val()
89 return _get_table_val(divider->table, div); in _get_val()
[all …]
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| /linux-6.12.1/drivers/clk/sophgo/ |
| D | clk-cv18xx-ip.c | 70 /* DIV */
88 struct cv1800_clk_div *div = hw_to_cv1800_clk_div(hw); in div_enable() local
90 return cv1800_clk_setbit(&div->common, &div->gate); in div_enable()
95 struct cv1800_clk_div *div = hw_to_cv1800_clk_div(hw); in div_disable() local
97 cv1800_clk_clearbit(&div->common, &div->gate); in div_disable()
102 struct cv1800_clk_div *div = hw_to_cv1800_clk_div(hw); in div_is_enabled() local
104 return cv1800_clk_checkbit(&div->common, &div->gate); in div_is_enabled()
108 struct cv1800_clk_regfield *div, in div_helper_set_rate() argument
114 if (div->width == 0) in div_helper_set_rate()
119 reg = readl(common->base + div->reg); in div_helper_set_rate()
[all …]
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| /linux-6.12.1/drivers/clk/ |
| D | clk-divider.c | 51 for (clkt = table; clkt->div; clkt++) in _get_table_maxdiv()
52 if (clkt->div > maxdiv && clkt->val <= mask) in _get_table_maxdiv()
53 maxdiv = clkt->div; in _get_table_maxdiv()
62 for (clkt = table; clkt->div; clkt++) in _get_table_mindiv()
63 if (clkt->div < mindiv) in _get_table_mindiv()
64 mindiv = clkt->div; in _get_table_mindiv()
85 for (clkt = table; clkt->div; clkt++) in _get_table_div()
87 return clkt->div; in _get_table_div()
106 unsigned int div) in _get_table_val() argument
110 for (clkt = table; clkt->div; clkt++) in _get_table_val()
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| D | clk-fsl-flexspi.c | 14 { .val = 0, .div = 1, },
15 { .val = 1, .div = 2, },
16 { .val = 2, .div = 3, },
17 { .val = 3, .div = 4, },
18 { .val = 4, .div = 5, },
19 { .val = 5, .div = 6, },
20 { .val = 6, .div = 7, },
21 { .val = 7, .div = 8, },
22 { .val = 11, .div = 12, },
23 { .val = 15, .div = 16, },
[all …]
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| D | clk-milbeaut.c | 83 u8 div; member
101 { .val = 0, .div = 8 },
102 { .val = 1, .div = 9 },
103 { .val = 2, .div = 10 },
104 { .val = 3, .div = 15 },
105 { .div = 0 },
109 { .val = 1, .div = 2 },
110 { .val = 3, .div = 4 },
111 { .div = 0 },
115 { .val = 3, .div = 4 },
[all …]
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| D | clk-cdce706.c | 29 #define CDCE706_DIVIDER(div) (13 + (div)) argument
50 #define CDCE706_DIVIDER_PLL(div) (9 + (div) - ((div) > 2) - ((div) > 4)) argument
51 #define CDCE706_DIVIDER_PLL_SHIFT(div) ((div) < 2 ? 5 : 3 * ((div) & 1)) argument
52 #define CDCE706_DIVIDER_PLL_MASK(div) (0x7 << CDCE706_DIVIDER_PLL_SHIFT(div)) argument
72 unsigned div; member
169 "%s, pll: %d, mux: %d, mul: %u, div: %u\n", in cdce706_pll_recalc_rate()
170 __func__, hwd->idx, hwd->mux, hwd->mul, hwd->div); in cdce706_pll_recalc_rate()
173 if (hwd->div && hwd->mul) { in cdce706_pll_recalc_rate()
176 do_div(res, hwd->div); in cdce706_pll_recalc_rate()
180 if (hwd->div) in cdce706_pll_recalc_rate()
[all …]
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| D | clk-fixed-factor.c | 18 * rate - rate is fixed. clk->rate = parent->rate / div * mult
29 do_div(rate, fix->div); in clk_factor_recalc_rate()
41 best_parent = (rate / fix->mult) * fix->div; in clk_factor_round_rate()
45 return (*prate / fix->div) * fix->mult; in clk_factor_round_rate()
95 unsigned long flags, unsigned int mult, unsigned int div, in __clk_hw_register_fixed_factor() argument
117 fix->div = div; in __clk_hw_register_fixed_factor()
158 * @div: divider
165 unsigned int mult, unsigned int div) in devm_clk_hw_register_fixed_factor_index() argument
170 flags, mult, div, 0, 0, true); in devm_clk_hw_register_fixed_factor_index()
182 * @div: divider
[all …]
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| /linux-6.12.1/drivers/clk/mxs/ |
| D | clk-div.c | 38 struct clk_div *div = to_clk_div(hw); in clk_div_recalc_rate() local
40 return div->ops->recalc_rate(&div->divider.hw, parent_rate); in clk_div_recalc_rate()
46 struct clk_div *div = to_clk_div(hw); in clk_div_round_rate() local
48 return div->ops->round_rate(&div->divider.hw, rate, prate); in clk_div_round_rate()
54 struct clk_div *div = to_clk_div(hw); in clk_div_set_rate() local
57 ret = div->ops->set_rate(&div->divider.hw, rate, parent_rate); in clk_div_set_rate()
59 ret = mxs_clk_wait(div->reg, div->busy); in clk_div_set_rate()
73 struct clk_div *div; in mxs_clk_div() local
77 div = kzalloc(sizeof(*div), GFP_KERNEL); in mxs_clk_div()
78 if (!div) in mxs_clk_div()
[all …]
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| /linux-6.12.1/drivers/clk/bcm/ |
| D | clk-iproc-asiu.c | 22 struct iproc_asiu_div div; member
82 val = readl(asiu->div_base + clk->div.offset); in iproc_asiu_clk_recalc_rate()
83 if ((val & (1 << clk->div.en_shift)) == 0) { in iproc_asiu_clk_recalc_rate()
89 div_h = (val >> clk->div.high_shift) & bit_mask(clk->div.high_width); in iproc_asiu_clk_recalc_rate()
91 div_l = (val >> clk->div.low_shift) & bit_mask(clk->div.low_width); in iproc_asiu_clk_recalc_rate()
104 unsigned int div; in iproc_asiu_clk_round_rate() local
112 div = DIV_ROUND_CLOSEST(*parent_rate, rate); in iproc_asiu_clk_round_rate()
113 if (div < 2) in iproc_asiu_clk_round_rate()
116 return *parent_rate / div; in iproc_asiu_clk_round_rate()
124 unsigned int div, div_h, div_l; in iproc_asiu_clk_set_rate() local
[all …]
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| /linux-6.12.1/Documentation/sphinx-static/ |
| D | custom.css | 7 div.body h1 { font-size: 180%; }
8 div.body h2 { font-size: 150%; }
9 div.body h3 { font-size: 130%; }
10 div.body h4 { font-size: 110%; }
13 div.toctree-wrapper p.caption[role=heading] { font-size: 150%; }
16 div.body { padding: 0 15px 0 10px; }
17 div.sphinxsidebarwrapper { padding: 1em 0.4em; }
18 div.sphinxsidebar { font-size: inherit;
22 div.document {
41 div.kernelindent { margin-left: 2em; margin-right: 4em; }
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| /linux-6.12.1/drivers/clk/meson/ |
| D | clk-regmap.c | 63 struct clk_regmap_div_data *div = clk_get_regmap_div_data(clk); in clk_regmap_div_recalc_rate() local
67 ret = regmap_read(clk->map, div->offset, &val); in clk_regmap_div_recalc_rate()
72 val >>= div->shift; in clk_regmap_div_recalc_rate()
73 val &= clk_div_mask(div->width); in clk_regmap_div_recalc_rate()
74 return divider_recalc_rate(hw, prate, val, div->table, div->flags, in clk_regmap_div_recalc_rate()
75 div->width); in clk_regmap_div_recalc_rate()
82 struct clk_regmap_div_data *div = clk_get_regmap_div_data(clk); in clk_regmap_div_determine_rate() local
87 if (div->flags & CLK_DIVIDER_READ_ONLY) { in clk_regmap_div_determine_rate()
88 ret = regmap_read(clk->map, div->offset, &val); in clk_regmap_div_determine_rate()
92 val >>= div->shift; in clk_regmap_div_determine_rate()
[all …]
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| /linux-6.12.1/Documentation/misc-devices/ |
| D | oxsemi-tornado.rst | 45 (tcr), the clock prescaler (cpr) and the divisor (div) produced by the
50 r: 15625000, a: 15625000.00, d: 0.0000%, tcr: 4, cpr: 1.000, div: 1
51 r: 12500000, a: 12500000.00, d: 0.0000%, tcr: 5, cpr: 1.000, div: 1
52 r: 10416666, a: 10416666.67, d: 0.0000%, tcr: 6, cpr: 1.000, div: 1
53 r: 8928571, a: 8928571.43, d: 0.0000%, tcr: 7, cpr: 1.000, div: 1
54 r: 7812500, a: 7812500.00, d: 0.0000%, tcr: 8, cpr: 1.000, div: 1
55 r: 4000000, a: 4000000.00, d: 0.0000%, tcr: 5, cpr: 3.125, div: 1
56 r: 3686400, a: 3676470.59, d: -0.2694%, tcr: 8, cpr: 2.125, div: 1
57 r: 3500000, a: 3496503.50, d: -0.0999%, tcr: 13, cpr: 1.375, div: 1
58 r: 3000000, a: 2976190.48, d: -0.7937%, tcr: 14, cpr: 1.500, div: 1
[all …]
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| /linux-6.12.1/drivers/clk/at91/ |
| D | clk-master.c | 39 u8 div; member
43 /* MCK div reference to be used by notifier. */
87 u8 div; in clk_master_div_recalc_rate() local
101 div = (mckr >> MASTER_DIV_SHIFT) & MASTER_DIV_MASK; in clk_master_div_recalc_rate()
103 rate /= characteristics->divisors[div]; in clk_master_div_recalc_rate()
106 pr_warn("master clk div is underclocked"); in clk_master_div_recalc_rate()
108 pr_warn("master clk div is overclocked"); in clk_master_div_recalc_rate()
118 unsigned int mckr, div; in clk_master_div_save_context() local
125 div = (mckr >> MASTER_DIV_SHIFT) & MASTER_DIV_MASK; in clk_master_div_save_context()
126 div = master->characteristics->divisors[div]; in clk_master_div_save_context()
[all …]
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| /linux-6.12.1/drivers/clk/sunxi/ |
| D | clk-sunxi.c | 35 u8 div; in sun4i_get_pll1_factors() local
38 div = req->rate / 6000000; in sun4i_get_pll1_factors()
39 req->rate = 6000000 * div; in sun4i_get_pll1_factors()
52 if (div < 10) in sun4i_get_pll1_factors()
56 else if (div < 20 || (div < 32 && (div & 1))) in sun4i_get_pll1_factors()
61 else if (div < 40 || (div < 64 && (div & 2))) in sun4i_get_pll1_factors()
69 div <<= req->p; in sun4i_get_pll1_factors()
70 div /= (req->k + 1); in sun4i_get_pll1_factors()
71 req->n = div / 4; in sun4i_get_pll1_factors()
159 u8 div; in sun8i_a23_get_pll1_factors() local
[all …]
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| /linux-6.12.1/drivers/clk/sprd/ |
| D | div.c | 10 #include "div.h"
18 cd->div.width, 0); in sprd_div_round_rate()
22 const struct sprd_div_internal *div, in sprd_div_helper_recalc_rate() argument
28 regmap_read(common->regmap, common->reg + div->offset, ®); in sprd_div_helper_recalc_rate()
29 val = reg >> div->shift; in sprd_div_helper_recalc_rate()
30 val &= (1 << div->width) - 1; in sprd_div_helper_recalc_rate()
33 div->width); in sprd_div_helper_recalc_rate()
42 return sprd_div_helper_recalc_rate(&cd->common, &cd->div, parent_rate); in sprd_div_recalc_rate()
46 const struct sprd_div_internal *div, in sprd_div_helper_set_rate() argument
54 div->width, 0); in sprd_div_helper_set_rate()
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| /linux-6.12.1/arch/mips/boot/dts/mobileye/ |
| D | eyeq5-clocks.dtsi | 21 clock-div = <1>;
28 clock-div = <1>;
35 clock-div = <1>;
42 clock-div = <1>;
49 clock-div = <1>;
56 clock-div = <1>;
63 clock-div = <1>;
70 clock-div = <1>;
77 clock-div = <1>;
84 clock-div = <2>;
[all …]
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| /linux-6.12.1/drivers/mmc/host/ |
| D | meson-mx-sdhc-clkc.c | 17 struct clk_divider div; member
32 { .div = 6, .val = 5, },
33 { .div = 8, .val = 7, },
34 { .div = 9, .val = 8, },
35 { .div = 10, .val = 9, },
36 { .div = 12, .val = 11, },
37 { .div = 16, .val = 15, },
38 { .div = 18, .val = 17, },
39 { .div = 34, .val = 33, },
40 { .div = 142, .val = 141, },
[all …]
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| /linux-6.12.1/drivers/clk/ingenic/ |
| D | cgu.c | 412 u32 div_reg, div; in ingenic_clk_recalc_rate() local
418 if (!(clk_info->div.bypass_mask & BIT(parent))) { in ingenic_clk_recalc_rate()
419 div_reg = readl(cgu->base + clk_info->div.reg); in ingenic_clk_recalc_rate()
420 div = (div_reg >> clk_info->div.shift) & in ingenic_clk_recalc_rate()
421 GENMASK(clk_info->div.bits - 1, 0); in ingenic_clk_recalc_rate()
423 if (clk_info->div.div_table) in ingenic_clk_recalc_rate()
424 div = clk_info->div.div_table[div]; in ingenic_clk_recalc_rate()
426 div = (div + 1) * clk_info->div.div; in ingenic_clk_recalc_rate()
428 rate /= div; in ingenic_clk_recalc_rate()
431 rate /= clk_info->fixdiv.div; in ingenic_clk_recalc_rate()
[all …]
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| /linux-6.12.1/drivers/clk/tegra/ |
| D | clk-divider.c | 24 int div; in get_div() local
26 div = div_frac_get(rate, parent_rate, divider->width, in get_div()
29 if (div < 0) in get_div()
32 return div; in get_div()
40 int div, mul; in clk_frac_div_recalc_rate() local
49 div = (reg >> divider->shift) & div_mask(divider); in clk_frac_div_recalc_rate()
52 div += mul; in clk_frac_div_recalc_rate()
55 rate += div - 1; in clk_frac_div_recalc_rate()
56 do_div(rate, div); in clk_frac_div_recalc_rate()
65 int div, mul; in clk_frac_div_round_rate() local
[all …]
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| /linux-6.12.1/drivers/clk/x86/ |
| D | clk-cgu.c | 165 struct lgm_clk_divider *div = to_lgm_clk_divider(hw); in lgm_clk_divider_enable_disable() local
167 if (div->flags != DIV_CLK_NO_MASK) in lgm_clk_divider_enable_disable()
168 lgm_set_clk_val(div->membase, div->reg, div->shift_gate, in lgm_clk_divider_enable_disable()
169 div->width_gate, enable); in lgm_clk_divider_enable_disable()
197 struct lgm_clk_divider *div; in lgm_clk_register_divider() local
207 div = devm_kzalloc(dev, sizeof(*div), GFP_KERNEL); in lgm_clk_register_divider()
208 if (!div) in lgm_clk_register_divider()
217 div->membase = ctx->membase; in lgm_clk_register_divider()
218 div->reg = reg; in lgm_clk_register_divider()
219 div->shift = shift; in lgm_clk_register_divider()
[all …]
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| /linux-6.12.1/drivers/clk/qcom/ |
| D | clk-regmap-mux-div.c | 12 #include "clk-regmap-mux-div.h"
23 int mux_div_set_src_div(struct clk_regmap_mux_div *md, u32 src, u32 div) in mux_div_set_src_div() argument
29 val = (div << md->hid_shift) | (src << md->src_shift); in mux_div_set_src_div()
60 u32 *div) in mux_div_get_src_div() argument
79 *div = d; in mux_div_get_src_div()
92 unsigned int i, div, max_div; in mux_div_determine_rate() local
101 for (div = 1; div < max_div; div++) { in mux_div_determine_rate()
102 parent_rate = mult_frac(req_rate, div, 2); in mux_div_determine_rate()
104 actual_rate = mult_frac(parent_rate, 2, div); in mux_div_determine_rate()
129 u32 div, max_div, best_src = 0, best_div = 0; in __mux_div_set_rate_and_parent() local
[all …]
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| /linux-6.12.1/drivers/clk/pistachio/ |
| D | clk-pistachio.c | 57 DIV(CLK_MIPS_INTERNAL_DIV, "mips_internal_div", "mips_pll_mux",
59 DIV(CLK_MIPS_DIV, "mips_div", "mips_internal_div", 0x208, 8),
68 DIV(CLK_RPU_V_DIV, "rpu_v_div", "rpu_v_pll_mux", 0x21c, 2),
69 DIV(CLK_RPU_L_DIV, "rpu_l_div", "rpu_l_mux", 0x220, 2),
70 DIV(CLK_RPU_SLEEP_DIV, "rpu_sleep_div", "xtal", 0x224, 10),
71 DIV(CLK_RPU_CORE_DIV, "rpu_core_div", "rpu_core_mux", 0x228, 3),
72 DIV(CLK_USB_PHY_DIV, "usb_phy_div", "sys_internal_div", 0x22c, 6),
73 DIV(CLK_ENET_DIV, "enet_div", "enet_mux", 0x230, 6),
82 DIV(CLK_SYS_INTERNAL_DIV, "sys_internal_div", "sys_pll_mux", 0x244, 3),
83 DIV(CLK_SPI0_INTERNAL_DIV, "spi0_internal_div", "sys_pll_mux",
[all …]
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