70 /* DIV */
88 	struct cv1800_clk_div *div = hw_to_cv1800_clk_div(hw);  in div_enable()  local
90 	return cv1800_clk_setbit(&div->common, &div->gate);  in div_enable()
95 	struct cv1800_clk_div *div = hw_to_cv1800_clk_div(hw);  in div_disable()  local
97 	cv1800_clk_clearbit(&div->common, &div->gate);  in div_disable()
102 	struct cv1800_clk_div *div = hw_to_cv1800_clk_div(hw);  in div_is_enabled()  local
104 	return cv1800_clk_checkbit(&div->common, &div->gate);  in div_is_enabled()
108 			       struct cv1800_clk_regfield *div,  in div_helper_set_rate()  argument
114 	if (div->width == 0)  in div_helper_set_rate()
119 	reg = readl(common->base + div->reg);  in div_helper_set_rate()
120 	reg = cv1800_clk_regfield_set(reg, val, div);  in div_helper_set_rate()
121 	if (div->initval > 0)  in div_helper_set_rate()
124 	writel(reg, common->base + div->reg);  in div_helper_set_rate()
132 				   struct cv1800_clk_regfield *div)  in div_helper_get_clockdiv()  argument
137 	if (!div || div->initval < 0 || (div->width == 0 && div->initval <= 0))  in div_helper_get_clockdiv()
140 	if (div->width == 0 && div->initval > 0)  in div_helper_get_clockdiv()
141 		return div->initval;  in div_helper_get_clockdiv()
143 	reg = readl(common->base + div->reg);  in div_helper_get_clockdiv()
145 	if (div->initval == 0 || DIV_GET_EN_CLK_DIV_FACTOR(reg))  in div_helper_get_clockdiv()
146 		clockdiv = cv1800_clk_regfield_get(reg, div);  in div_helper_get_clockdiv()
147 	else if (div->initval > 0)  in div_helper_get_clockdiv()
148 		clockdiv = div->initval;  in div_helper_get_clockdiv()
153 static u32 div_helper_round_rate(struct cv1800_clk_regfield *div,  in div_helper_round_rate()  argument
157 	if (div->width == 0) {  in div_helper_round_rate()
158 		if (div->initval <= 0)  in div_helper_round_rate()
161 			return DIV_ROUND_UP_ULL(*prate, div->initval);  in div_helper_round_rate()
165 					 div->width, div->flags);  in div_helper_round_rate()
171 	struct cv1800_clk_div *div = data;  in div_round_rate()  local
173 	return div_helper_round_rate(&div->div, &div->common.hw, parent,  in div_round_rate()
252 	struct cv1800_clk_div *div = hw_to_cv1800_clk_div(hw);  in div_determine_rate()  local
254 	return mux_helper_determine_rate(&div->common, req,  in div_determine_rate()
255 					 div_round_rate, div);  in div_determine_rate()
261 	struct cv1800_clk_div *div = hw_to_cv1800_clk_div(hw);  in div_recalc_rate()  local
264 	val = div_helper_get_clockdiv(&div->common, &div->div);  in div_recalc_rate()
269 				   div->div.flags, div->div.width);  in div_recalc_rate()
275 	struct cv1800_clk_div *div = hw_to_cv1800_clk_div(hw);  in div_set_rate()  local
279 			      div->div.width, div->div.flags);  in div_set_rate()
281 	return div_helper_set_rate(&div->common, &div->div, val);  in div_set_rate()
297 	struct cv1800_clk_div *div = hw_to_cv1800_clk_div(hw);  in hw_to_cv1800_clk_bypass_div()  local
299 	return container_of(div, struct cv1800_clk_bypass_div, div);  in hw_to_cv1800_clk_bypass_div()
306 	struct cv1800_clk_bypass_div *div = data;  in bypass_div_round_rate()  local
309 		if (cv1800_clk_checkbit(&div->div.common, &div->bypass))  in bypass_div_round_rate()
313 					      -1, &div->div);  in bypass_div_round_rate()
319 	return div_round_rate(parent, parent_rate, rate, id - 1, &div->div);  in bypass_div_round_rate()
325 	struct cv1800_clk_bypass_div *div = hw_to_cv1800_clk_bypass_div(hw);  in bypass_div_determine_rate()  local
327 	return mux_helper_determine_rate(&div->div.common, req,  in bypass_div_determine_rate()
328 					 bypass_div_round_rate, div);  in bypass_div_determine_rate()
334 	struct cv1800_clk_bypass_div *div = hw_to_cv1800_clk_bypass_div(hw);  in bypass_div_recalc_rate()  local
336 	if (cv1800_clk_checkbit(&div->div.common, &div->bypass))  in bypass_div_recalc_rate()
345 	struct cv1800_clk_bypass_div *div = hw_to_cv1800_clk_bypass_div(hw);  in bypass_div_set_rate()  local
347 	if (cv1800_clk_checkbit(&div->div.common, &div->bypass))  in bypass_div_set_rate()
355 	struct cv1800_clk_bypass_div *div = hw_to_cv1800_clk_bypass_div(hw);  in bypass_div_get_parent()  local
357 	if (cv1800_clk_checkbit(&div->div.common, &div->bypass))  in bypass_div_get_parent()
365 	struct cv1800_clk_bypass_div *div = hw_to_cv1800_clk_bypass_div(hw);  in bypass_div_set_parent()  local
368 		return cv1800_clk_clearbit(&div->div.common, &div->bypass);  in bypass_div_set_parent()
370 	return cv1800_clk_setbit(&div->div.common, &div->bypass);  in bypass_div_set_parent()
420 	return div_helper_round_rate(&mux->div, &mux->common.hw, parent,  in mux_round_rate()
439 	val = div_helper_get_clockdiv(&mux->common, &mux->div);  in mux_recalc_rate()
444 				   mux->div.flags, mux->div.width);  in mux_recalc_rate()
454 			      mux->div.width, mux->div.flags);  in mux_set_rate()
456 	return div_helper_set_rate(&mux->common, &mux->div, val);  in mux_set_rate()
658 	return div_helper_round_rate(&mmux->div[div_id],  in mmux_round_rate()
677 	struct cv1800_clk_regfield *div;  in mmux_recalc_rate()  local
683 		div = &mmux->div[0];  in mmux_recalc_rate()
685 		div = &mmux->div[1];  in mmux_recalc_rate()
687 	val = div_helper_get_clockdiv(&mmux->common, div);  in mmux_recalc_rate()
692 				   div->flags, div->width);  in mmux_recalc_rate()
699 	struct cv1800_clk_regfield *div;  in mmux_set_rate()  local
706 		div = &mmux->div[0];  in mmux_set_rate()
708 		div = &mmux->div[1];  in mmux_set_rate()
711 			      div->width, div->flags);  in mmux_set_rate()
713 	return div_helper_set_rate(&mmux->common, div, val);  in mmux_set_rate()