18  * rate - rate is fixed.  clk->rate = parent->rate / div * mult
29 	do_div(rate, fix->div);  in clk_factor_recalc_rate()
41 		best_parent = (rate / fix->mult) * fix->div;  in clk_factor_round_rate()
45 	return (*prate / fix->div) * fix->mult;  in clk_factor_round_rate()
95 		unsigned long flags, unsigned int mult, unsigned int div,  in __clk_hw_register_fixed_factor()  argument
117 	fix->div = div;  in __clk_hw_register_fixed_factor()
158  * @div: divider
165 		unsigned int mult, unsigned int div)  in devm_clk_hw_register_fixed_factor_index()  argument
170 					      flags, mult, div, 0, 0, true);  in devm_clk_hw_register_fixed_factor_index()
182  * @div: divider
189 		unsigned long flags, unsigned int mult, unsigned int div)  in devm_clk_hw_register_fixed_factor_parent_hw()  argument
194 					      &pdata, flags, mult, div, 0, 0, true);  in devm_clk_hw_register_fixed_factor_parent_hw()
200 		unsigned long flags, unsigned int mult, unsigned int div)  in clk_hw_register_fixed_factor_parent_hw()  argument
205 					      &pdata, flags, mult, div, 0, 0, false);  in clk_hw_register_fixed_factor_parent_hw()
211 		unsigned int mult, unsigned int div)  in clk_hw_register_fixed_factor()  argument
216 					      &pdata, flags, mult, div, 0, 0, false);  in clk_hw_register_fixed_factor()
222 		unsigned long flags, unsigned int mult, unsigned int div)  in clk_hw_register_fixed_factor_fwname()  argument
227 			&pdata, flags, mult, div, 0, 0, false);  in clk_hw_register_fixed_factor_fwname()
233 		unsigned long flags, unsigned int mult, unsigned int div,  in clk_hw_register_fixed_factor_with_accuracy_fwname()  argument
239 			&pdata, flags, mult, div, acc,  in clk_hw_register_fixed_factor_with_accuracy_fwname()
246 		unsigned int mult, unsigned int div)  in clk_register_fixed_factor()  argument
251 					  div);  in clk_register_fixed_factor()
284 		unsigned int mult, unsigned int div)  in devm_clk_hw_register_fixed_factor()  argument
289 			&pdata, flags, mult, div, 0, 0, true);  in devm_clk_hw_register_fixed_factor()
295 		unsigned long flags, unsigned int mult, unsigned int div)  in devm_clk_hw_register_fixed_factor_fwname()  argument
300 			&pdata, flags, mult, div, 0, 0, true);  in devm_clk_hw_register_fixed_factor_fwname()
306 		unsigned long flags, unsigned int mult, unsigned int div,  in devm_clk_hw_register_fixed_factor_with_accuracy_fwname()  argument
312 			&pdata, flags, mult, div, acc,  in devm_clk_hw_register_fixed_factor_with_accuracy_fwname()
323 	u32 div, mult;  in _of_fixed_factor_clk_setup()  local
326 	if (of_property_read_u32(node, "clock-div", &div)) {  in _of_fixed_factor_clk_setup()
327 		pr_err("%s Fixed factor clock <%pOFn> must have a clock-div property\n",  in _of_fixed_factor_clk_setup()
341 					    &pdata, 0, mult, div, 0, 0, false);  in _of_fixed_factor_clk_setup()