Lines Matching full:div
39 u8 div; member
43 /* MCK div reference to be used by notifier. */
87 u8 div; in clk_master_div_recalc_rate() local
101 div = (mckr >> MASTER_DIV_SHIFT) & MASTER_DIV_MASK; in clk_master_div_recalc_rate()
103 rate /= characteristics->divisors[div]; in clk_master_div_recalc_rate()
106 pr_warn("master clk div is underclocked"); in clk_master_div_recalc_rate()
108 pr_warn("master clk div is overclocked"); in clk_master_div_recalc_rate()
118 unsigned int mckr, div; in clk_master_div_save_context() local
125 div = (mckr >> MASTER_DIV_SHIFT) & MASTER_DIV_MASK; in clk_master_div_save_context()
126 div = master->characteristics->divisors[div]; in clk_master_div_save_context()
129 master->pms.rate = DIV_ROUND_CLOSEST(master->pms.parent_rate, div); in clk_master_div_save_context()
139 u8 div; in clk_master_div_restore_context() local
146 div = (mckr >> MASTER_DIV_SHIFT) & MASTER_DIV_MASK; in clk_master_div_restore_context()
147 div = master->characteristics->divisors[div]; in clk_master_div_restore_context()
149 if (div != DIV_ROUND_CLOSEST(master->pms.parent_rate, master->pms.rate)) in clk_master_div_restore_context()
150 pr_warn("MCKR DIV not configured properly by firmware!\n"); in clk_master_div_restore_context()
163 unsigned long parent_rate, int div) in clk_master_div_set() argument
176 if (div == characteristics->divisors[i]) in clk_master_div_set()
185 if (div > max_div) in clk_master_div_set()
199 pr_warn("master clk div is underclocked"); in clk_master_div_set()
201 pr_warn("master clk div is overclocked"); in clk_master_div_set()
212 master->div = characteristics->divisors[div_index]; in clk_master_div_set()
222 return DIV_ROUND_CLOSEST_ULL(parent_rate, master->div); in clk_master_div_recalc_rate_chg()
237 pr_warn("Failed to restore MCK DIV clock\n"); in clk_master_div_restore_context_chg()
255 unsigned int mckr, div, new_div = 0; in clk_master_div_notifier_fn() local
264 * We want to avoid any overclocking of MCK DIV domain. To do in clk_master_div_notifier_fn()
269 * FRAC PLL -> DIV PLL -> MCK DIV in clk_master_div_notifier_fn()
282 div = (mckr >> MASTER_DIV_SHIFT) & MASTER_DIV_MASK; in clk_master_div_notifier_fn()
286 cnd->old_rate * characteristics->divisors[div], in clk_master_div_notifier_fn()
292 * At this point we want to restore MCK DIV domain to its maximum in clk_master_div_notifier_fn()
303 div = (mckr >> MASTER_DIV_SHIFT) & MASTER_DIV_MASK; in clk_master_div_notifier_fn()
304 new_parent_rate = cnd->new_rate * characteristics->divisors[div]; in clk_master_div_notifier_fn()
331 /* Update the div to preserve MCK DIV clock rate. */ in clk_master_div_notifier_fn()
358 u32 div) in clk_sama7g5_master_best_diff() argument
362 if (div == MASTER_PRES_MAX) in clk_sama7g5_master_best_diff()
365 tmp_rate = parent_rate >> div; in clk_sama7g5_master_best_diff()
517 master->div = characteristics->divisors[mckr]; in at91_clk_register_master_internal()
583 return DIV_ROUND_CLOSEST_ULL(parent_rate, (1 << master->div)); in clk_sama7g5_master_recalc_rate()
593 unsigned int div, i; in clk_sama7g5_master_determine_rate() local
605 for (div = 0; div < MASTER_PRES_MAX + 1; div++) { in clk_sama7g5_master_determine_rate()
608 div); in clk_sama7g5_master_determine_rate()
625 for (div = 0; div < MASTER_PRES_MAX + 1; div++) { in clk_sama7g5_master_determine_rate()
629 if (div == MASTER_PRES_MAX) in clk_sama7g5_master_determine_rate()
632 req_rate = req->rate << div; in clk_sama7g5_master_determine_rate()
639 &best_rate, &best_diff, div); in clk_sama7g5_master_determine_rate()
695 unsigned int div = master->div << MASTER_DIV_SHIFT; in clk_sama7g5_master_set() local
705 enable | parent | div | AT91_PMC_MCR_V2_CMD | in clk_sama7g5_master_set()
763 unsigned long div, flags; in clk_sama7g5_master_set_rate() local
765 div = DIV_ROUND_CLOSEST(parent_rate, rate); in clk_sama7g5_master_set_rate()
766 if ((div > (1 << (MASTER_PRES_MAX - 1))) || (div & (div - 1))) in clk_sama7g5_master_set_rate()
769 if (div == 3) in clk_sama7g5_master_set_rate()
770 div = MASTER_PRES_MAX; in clk_sama7g5_master_set_rate()
771 else if (div) in clk_sama7g5_master_set_rate()
772 div = ffs(div) - 1; in clk_sama7g5_master_set_rate()
775 master->div = div; in clk_sama7g5_master_set_rate()
859 master->div = (val & AT91_PMC_MCR_V2_DIV) >> MASTER_DIV_SHIFT; in at91_clk_sama7g5_register_master()