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/linux-6.12.1/Documentation/devicetree/bindings/phy/
Dapm-xgene-phy.txt1 * APM X-Gene 15Gbps Multi-purpose PHY nodes
3 PHY nodes are defined to describe on-chip 15Gbps Multi-purpose PHY. Each
48 0 = 1-2Gbps
49 1 = 2-4Gbps (1st tuple default)
50 2 = 4-8Gbps
51 3 = 8-15Gbps (2nd tuple default)
52 4 = 2.5-4Gbps
53 5 = 4-5Gbps
54 6 = 5-6Gbps
55 7 = 6-16Gbps (3rd tuple default)
/linux-6.12.1/drivers/scsi/mvsas/
Dmv_94xx.h147 MVS_IRQ_COM_OUT_I2O_HOS2 = (1 << 6),
180 * bit 2: 6Gbps support
181 * bit 1: 3Gbps support
182 * bit 0: 1.5Gbps support
188 * bit 5: G1 (1.5Gbps) Without SSC
189 * bit 4: G1 (1.5Gbps) with SSC
190 * bit 3: G2 (3.0Gbps) Without SSC
191 * bit 2: G2 (3.0Gbps) with SSC
192 * bit 1: G3 (6.0Gbps) without SSC
193 * bit 0: G3 (6.0Gbps) with SSC
[all …]
Dmv_94xx.c111 * FFE_RES_SEL [6:4] in set_phy_ffe_tuning()
139 * DFE_UPDATE_EN [11:6] in set_phy_ffe_tuning()
147 tmp |= ((0x3F << 6) | (0x0 << 0)); in set_phy_ffe_tuning()
177 /* support 1.5 Gbps */ in set_phy_rate()
185 /* support 1.5, 3.0 Gbps */ in set_phy_rate()
192 /* support 1.5, 3.0, 6.0 Gbps */ in set_phy_rate()
233 /*set default phy_rate = 6Gbps*/ in mvs_94xx_config_reg_from_hba()
408 /* set 6G/3G/1.5G, multiplexing, without SSC */ in mvs_94xx_init()
411 /* set 6G/3G/1.5G, multiplexing, with and without SSC */ in mvs_94xx_init()
/linux-6.12.1/drivers/gpu/drm/amd/display/dc/
Ddc_dp_types.h50 LINK_RATE_LOW = 0x06, // Rate_1 (RBR) - 1.62 Gbps/Lane
51 LINK_RATE_RATE_2 = 0x08, // Rate_2 - 2.16 Gbps/Lane
52 LINK_RATE_RATE_3 = 0x09, // Rate_3 - 2.43 Gbps/Lane
53 LINK_RATE_HIGH = 0x0A, // Rate_4 (HBR) - 2.70 Gbps/Lane
54 LINK_RATE_RBR2 = 0x0C, // Rate_5 (RBR2) - 3.24 Gbps/Lane
55 LINK_RATE_RATE_6 = 0x10, // Rate_6 - 4.32 Gbps/Lane
56 LINK_RATE_HIGH2 = 0x14, // Rate_7 (HBR2) - 5.40 Gbps/Lane
57 LINK_RATE_RATE_8 = 0x19, // Rate_8 - 6.75 Gbps/Lane
58 LINK_RATE_HIGH3 = 0x1E, // Rate_9 (HBR3) - 8.10 Gbps/Lane
62 LINK_RATE_UHBR10 = 1000, // UHBR10 - 10.0 Gbps/Lane
[all …]
/linux-6.12.1/Documentation/devicetree/bindings/media/i2c/
Dmaxim,max96712.yaml21 Each GMSL2 serial link operates at a fixed rate of 3Gbps or 6Gbps in the
23 MAX96712 can be paired with first-generation 3.12Gbps or 1.5Gbps GMSL1
24 serializers or operate up to 3.12Gbps with GMSL2 serializers in GMSL1 mode.
Dmaxim,max96717.yaml25 The GMSL2 serial link operates at a fixed rate of 3Gbps or 6Gbps in the
27 MAX96717F only supports a fixed rate of 3Gbps in the forward direction.
Dmaxim,max96714.yaml23 The GMSL2 serial link operates at a fixed rate of 3Gbps or 6Gbps in the
25 MAX96714F only supports a fixed rate of 3Gbps in the forward direction.
/linux-6.12.1/drivers/net/ethernet/ezchip/
Dnps_enet.h59 /* Gbps Eth MAC Configuration 0 register masks and shifts */
73 #define CFG_0_RX_CRC_STRIP_SHIFT 6
93 /* Gbps Eth MAC Configuration 1 register masks and shifts */
103 /* Gbps Eth MAC Configuration 2 register masks and shifts */
119 /* Gbps Eth MAC Configuration 3 register masks and shifts */
131 #define CFG_3_CF_TIMEOUT_SHIFT 6
/linux-6.12.1/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/
Dsmu11_driver_if_arcturus.h62 #define FEATURE_DPM_XGMI_BIT 6
193 #define THROTTLER_TEMP_VR_SOC_BIT 6
429 XGMI_LINK_RATE_2 = 2, // 2Gbps
430 XGMI_LINK_RATE_4 = 4, // 4Gbps
431 XGMI_LINK_RATE_8 = 8, // 8Gbps
432 XGMI_LINK_RATE_12 = 12, // 12Gbps
433 XGMI_LINK_RATE_16 = 16, // 16Gbps
434 XGMI_LINK_RATE_17 = 17, // 17Gbps
435 XGMI_LINK_RATE_18 = 18, // 18Gbps
436 XGMI_LINK_RATE_19 = 19, // 19Gbps
[all …]
Dsmu11_driver_if_sienna_cichlid.h51 #define NUM_OD_FAN_MAX_POINTS 6
82 #define FEATURE_DPM_MP0CLK_BIT 6
201 #define THROTTLER_TEMP_VR_MEM1_BIT 6
225 #define FW_DSTATE_MP1_WHISPER_MODE_BIT 6
524 XGMI_LINK_RATE_2 = 2, // 2Gbps
525 XGMI_LINK_RATE_4 = 4, // 4Gbps
526 XGMI_LINK_RATE_8 = 8, // 8Gbps
527 XGMI_LINK_RATE_12 = 12, // 12Gbps
528 XGMI_LINK_RATE_16 = 16, // 16Gbps
529 XGMI_LINK_RATE_17 = 17, // 17Gbps
[all …]
Dsmu13_driver_if_aldebaran.h44 #define FEATURE_DPM_XGMI_BIT 6
117 #define THROTTLER_TEMP_GPU_BIT 6
358 uint8_t XgmiLinkSpeed[NUM_XGMI_DPM_LEVELS]; //Gbps [EX: 32 = 32Gbps]
553 #define TABLE_I2C_COMMANDS 6
/linux-6.12.1/tools/testing/selftests/drivers/net/mlxsw/
Dqos_ets_strict.sh24 # | >1Gbps | | >1Gbps |
33 # | | 1Gbps bottleneck |
53 NUM_NETIFS=6
119 lldptool -T -i $swp3 -V ETS-CFG up2tc=0:0,1:1,2:2,3:3,4:4,5:5,6:6,7:7
127 )"6:strict,"$(
161 devlink_port_pool_th_set $swp1 0 6
163 devlink_tc_bind_pool_th_set $swp1 1 ingress 0 6
166 devlink_port_pool_th_set $swp2 0 6
168 devlink_tc_bind_pool_th_set $swp2 2 ingress 0 6
204 lldptool -T -i $swp3 -V ETS-CFG up2tc=0:0,1:0,2:0,3:0,4:0,5:0,6:0,7:0
Dqos_mc_aware.sh39 # | >1Gbps | | >1Gbps |
48 # | | 1Gbps bottleneck |
68 NUM_NETIFS=6
267 # degradation on 1Gbps link.
/linux-6.12.1/drivers/gpu/drm/i915/display/
Dintel_cx0_phy.c91 * It is required that PSR and DC5/6 are disabled before any CX0 message
425 return 6; in intel_c10_get_tx_term_ctl()
517 .pll[6] = 0x98,
543 .pll[6] = 0x75,
569 .pll[6] = 0xE3,
595 .pll[6] = 0x29,
621 .pll[6] = 0x98,
647 .pll[6] = 0x75,
673 .pll[6] = 0x29,
699 .pll[6] = 0x33,
[all …]
/linux-6.12.1/include/rdma/
Dopa_port_info.h33 #define OPA_LINKDOWN_REASON_BAD_DLID 6
96 #define OPA_LINK_SPEED_NOP 0x0000 /* Reserved (1-5 Gbps) */
97 #define OPA_LINK_SPEED_12_5G 0x0001 /* 12.5 Gbps */
98 #define OPA_LINK_SPEED_25G 0x0002 /* 25.78125? Gbps (EDR) */
107 #define OPA_CAP_MASK3_IsAsyncSC2VLSupported (1 << 6)
216 OPA_PI_MASK_BUF_UNIT_VL15_CREDIT_RATE = (0x0000001F << 6),
242 u8 ledenable_offlinereason; /* 1 res, 1 bit, 6 bits */
/linux-6.12.1/drivers/net/ethernet/hisilicon/hns3/hns3pf/
Dhclge_main.h116 #define HCLGE_PHY_MDIX_CTRL_M GENMASK(6, 5)
118 #define HCLGE_PHY_MDIX_STATUS_B 6
160 #define HCLGE_VECTOR0_CORERESET_INT_B 6
171 #define HCLGE_VECTOR0_ALL_MSIX_ERR_B 6U
194 #define HCLGE_SUPPORT_100M_BIT BIT(6)
247 HCLGE_MAC_SPEED_1G = 1000, /* 1000 Mbps = 1 Gbps */
248 HCLGE_MAC_SPEED_10G = 10000, /* 10000 Mbps = 10 Gbps */
249 HCLGE_MAC_SPEED_25G = 25000, /* 25000 Mbps = 25 Gbps */
250 HCLGE_MAC_SPEED_40G = 40000, /* 40000 Mbps = 40 Gbps */
251 HCLGE_MAC_SPEED_50G = 50000, /* 50000 Mbps = 50 Gbps */
[all …]
/linux-6.12.1/arch/arm64/boot/dts/marvell/
Darmada-8040-puzzle-m801.dts97 gpios = <&cp1_gpio1 6 GPIO_ACTIVE_LOW>;
108 /* SFP+ port 2: 10 Gbps indicator */
115 /* SFP+ port 2: 1 Gbps indicator */
122 /* SFP+ port 1: 10 Gbps indicator */
129 /* SFP+ port 1: 1 Gbps indicator */
135 led-6 {
/linux-6.12.1/drivers/usb/host/
Dxhci-hub.c25 0x00050034, /* USB 3.0 SS Gen1x1 id:4 symmetric rx 5Gbps */
26 0x000500b4, /* USB 3.0 SS Gen1x1 id:4 symmetric tx 5Gbps */
27 0x000a4035, /* USB 3.1 SSP Gen2x1 id:5 symmetric rx 10Gbps */
28 0x000a40b5, /* USB 3.1 SSP Gen2x1 id:5 symmetric tx 10Gbps */
29 0x00054036, /* USB 3.2 SSP Gen1x2 id:6 symmetric rx 5Gbps */
30 0x000540b6, /* USB 3.2 SSP Gen1x2 id:6 symmetric tx 5Gbps */
31 0x000a4037, /* USB 3.2 SSP Gen2x2 id:7 symmetric rx 10Gbps */
32 0x000a40b7, /* USB 3.2 SSP Gen2x2 id:7 symmetric tx 10Gbps */
169 /* Shift to Gbps and set SSP Link Protocol if 10Gpbs */ in xhci_create_usb3x_bos_desc()
186 * is 20Gbps, but the BOS descriptor lane speed mantissa is in xhci_create_usb3x_bos_desc()
[all …]
/linux-6.12.1/drivers/gpu/drm/amd/display/dc/link/protocols/
Dlink_dp_capability.c148 case 0x04: // 6 lttpr repeaters in dp_parse_lttpr_repeater_count()
149 return 6; in dp_parse_lttpr_repeater_count()
183 // LinkRate is normally stored as a multiplier of 0.27 Gbps per lane. Do the translation. in linkRateInKHzToLinkRateMultiplier()
186 link_rate = LINK_RATE_LOW; // Rate_1 (RBR) - 1.62 Gbps/Lane in linkRateInKHzToLinkRateMultiplier()
189 link_rate = LINK_RATE_RATE_2; // Rate_2 - 2.16 Gbps/Lane in linkRateInKHzToLinkRateMultiplier()
192 link_rate = LINK_RATE_RATE_3; // Rate_3 - 2.43 Gbps/Lane in linkRateInKHzToLinkRateMultiplier()
195 link_rate = LINK_RATE_HIGH; // Rate_4 (HBR) - 2.70 Gbps/Lane in linkRateInKHzToLinkRateMultiplier()
198 link_rate = LINK_RATE_RBR2; // Rate_5 (RBR2)- 3.24 Gbps/Lane in linkRateInKHzToLinkRateMultiplier()
201 link_rate = LINK_RATE_RATE_6; // Rate_6 - 4.32 Gbps/Lane in linkRateInKHzToLinkRateMultiplier()
204 link_rate = LINK_RATE_HIGH2; // Rate_7 (HBR2)- 5.40 Gbps/Lane in linkRateInKHzToLinkRateMultiplier()
[all …]
/linux-6.12.1/drivers/phy/marvell/
Dphy-mvebu-a3700-comphy.c102 #define GS2_RSVD_6_0_MASK GENMASK(6, 0)
111 #define TXDCLK_2X_SEL BIT(6)
136 #define TX_DET_RX_MODE BIT(6)
300 /* 0 1 2 3 4 5 6 7 */
583 * reg_set(MVEBU_REGS_BASE + 0xe00a4, BIT(6), BIT(6)); in mvebu_a3700_comphy_sata_power_on()
608 * All PHY register values are defined in full for 3.125Gbps in comphy_gbe_phy_init()
609 * SERDES speed. The values required for 1.25 Gbps are almost in comphy_gbe_phy_init()
611 * comparison to 3.125 Gbps values. These register values are in comphy_gbe_phy_init()
681 * 6. Wait 10mS for bandgap and reference clocks to stabilize; then in mvebu_a3700_comphy_ethernet_power_on()
715 * (not SERDES). For instance, it selects SATA speed 1.5/3/6 Gbps or in mvebu_a3700_comphy_ethernet_power_on()
[all …]
/linux-6.12.1/drivers/phy/mediatek/
Dphy-mtk-hdmi-mt8195.c33 /* HDMI 2.0 specification, 3.4Gbps <= TMDS Bit Rate <= 6G, in mtk_phy_tmds_clk_ratio()
34 * clock bit ratio 1:40, under 3.4Gbps, clock bit ratio 1:10 in mtk_phy_tmds_clk_ratio()
121 case 6: in mtk_hdmi_pll_set_hw()
170 case 6: in mtk_hdmi_pll_set_hw()
214 u8 txpredivs[4] = { 2, 4, 6, 12 }; in mtk_hdmi_pll_calc()
249 /* calculate txprediv: can be 2, 4, 6, 12 in mtk_hdmi_pll_calc()
312 * 3G < data rate <= 6G: enable impedance 100ohm, in mtk_hdmi_pll_drv_setting()
321 /* 3G < data rate <= 6G, 300M < tmds rate <= 594M */ in mtk_hdmi_pll_drv_setting()
/linux-6.12.1/drivers/net/ethernet/ibm/ehea/
Dehea_phyp.h116 #define H_QPCB1_SGEL_NB_RQ2 EHEA_BMASK_IBM(6, 6)
163 #define H_PORT_CB6 6
190 #define H_SPEED_1G_F 6 /* 1 Gbps, Full Duplex */
191 #define H_SPEED_10G_F 8 /* 10 Gbps, Full Duplex */
/linux-6.12.1/drivers/ata/
DKconfig49 This option will enlarge the kernel by approx. 6KB. Disable it only
269 tristate "APM X-Gene 6.0Gbps AHCI SATA host controller support"
287 tristate "Freescale 3.0Gbps SATA support"
291 This option enables support for Freescale 3.0Gbps SATA controller.
308 tristate "AMD Seattle 6.0Gbps AHCI SATA host controller support"
421 This option enables support for ICH5/6/7/8 Serial ATA
/linux-6.12.1/drivers/gpu/drm/kmb/
Dkmb_dsi.c310 data_type_param.size_constraint_bytes = 6; in mipi_get_datatype_params()
841 data = ((freq >> 6) & 0x1f) | (1 << 7); in set_test_mode_src_osc_freq_target_hi_bits()
930 * PLL_VCO_Control[6] = pll_vco_cntrl_ovr_en in mipi_tx_pll_setup()
933 | (1 << 6))); in mipi_tx_pll_setup()
1015 /* BitRate: > 1 Gbps && <= 1.5 Gbps: - slew rate control ON in set_slewrate_gt_1000()
1020 * bits[1:0}=srcal_en_ovr_en, srcal_en_ovr, bit[6]=sr_range in set_slewrate_gt_1000()
1023 test_data = (0x03 | (1 << 6)); in set_slewrate_gt_1000()
1031 /* Set sr_osc_freq_target[6:0] low nibble in set_slewrate_gt_1000()
1042 test_data = ((0x72f >> 6) & 0x1f) | (1 << 7); in set_slewrate_gt_1000()
1051 * BitRate: <= 1 Gbps: in set_slewrate_lt_1000()
[all …]
/linux-6.12.1/include/uapi/linux/
Dmdio.h24 #define MDIO_MMD_TC 6 /* Transmission Convergence */
38 #define MDIO_DEVS2 6
250 #define MDIO_AN_C73_1_10GBASE_KX4 BIT(6)
481 #define MDIO_USXGMII_10G 0x0600 /* 10Gbps */
482 #define MDIO_USXGMII_10GHALF 0x0600 /* 10Gbps half-duplex */
483 #define MDIO_USXGMII_10GFULL 0x1600 /* 10Gbps full-duplex */

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