Lines Matching +full:6 +full:gbps

102 #define GS2_RSVD_6_0_MASK		GENMASK(6, 0)
111 #define TXDCLK_2X_SEL			BIT(6)
136 #define TX_DET_RX_MODE			BIT(6)
300 	/* 0       1       2       3       4       5       6       7 */
583 	 *   reg_set(MVEBU_REGS_BASE + 0xe00a4, BIT(6), BIT(6));  in mvebu_a3700_comphy_sata_power_on()
608 		 * All PHY register values are defined in full for 3.125Gbps  in comphy_gbe_phy_init()
609 		 * SERDES speed. The values required for 1.25 Gbps are almost  in comphy_gbe_phy_init()
611 		 * comparison to 3.125 Gbps values. These register values are  in comphy_gbe_phy_init()
681 	 * 6. Wait 10mS for bandgap and reference clocks to stabilize; then  in mvebu_a3700_comphy_ethernet_power_on()
715 	 * (not SERDES). For instance, it selects SATA speed 1.5/3/6 Gbps or  in mvebu_a3700_comphy_ethernet_power_on()
716 	 * PCIe speed 2.5/5 Gbps  in mvebu_a3700_comphy_ethernet_power_on()
882 	 * 6. Set G2 Spread Spectrum Clock Amplitude at 4K  in mvebu_a3700_comphy_usb3_power_on()
956 	 * 14. Set max speed generation to USB3.0 5Gbps  in mvebu_a3700_comphy_usb3_power_on()
1018 	/* 6. Enable the output of 100M/125M/500M clock */  in mvebu_a3700_comphy_pcie_power_on()