Lines Matching +full:6 +full:gbps
91 * It is required that PSR and DC5/6 are disabled before any CX0 message
425 return 6; in intel_c10_get_tx_term_ctl()
517 .pll[6] = 0x98,
543 .pll[6] = 0x75,
569 .pll[6] = 0xE3,
595 .pll[6] = 0x29,
621 .pll[6] = 0x98,
647 .pll[6] = 0x75,
673 .pll[6] = 0x29,
699 .pll[6] = 0x33,
725 .pll[6] = 0x3D,
865 .clock = 1000000, /* 10 Gbps */
889 .clock = 1350000, /* 13.5 Gbps */
914 .clock = 2000000, /* 20 Gbps */
1091 .clock = 1350000, /* 13.5 Gbps */
1139 .pll[6] = 0,
1165 .pll[6] = 0,
1191 .pll[6] = 0,
1217 .pll[6] = 0,
1243 .pll[6] = 0,
1265 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
1275 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
1285 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
1295 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
1305 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
1315 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
1325 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
1335 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
1345 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
1355 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
1365 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
1375 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
1385 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
1395 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
1405 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
1415 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
1425 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
1435 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
1445 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
1455 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
1465 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
1475 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
1485 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
1495 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
1505 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
1515 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
1525 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
1535 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
1545 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
1555 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
1565 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
1575 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
1585 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
1595 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
1605 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
1615 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
1625 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
1635 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
1645 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
1655 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
2204 pll_state->mpllb[6] = (C20_MPLLB_FRACEN | SSC_UP_SPREAD); in intel_c20_compute_hdmi_tmds_pll()
2316 frac_en = REG_FIELD_GET(C20_MPLLB_FRACEN, pll_state->mpllb[6]); in intel_c20pll_calc_port_clock()
2322 ref_clk_mpllb_div = REG_FIELD_GET(C20_REF_CLK_MPLLB_DIV_MASK, pll_state->mpllb[6]); in intel_c20pll_calc_port_clock()
2326 frac_en = REG_FIELD_GET(C20_MPLLA_FRACEN, pll_state->mplla[6]); in intel_c20pll_calc_port_clock()
2332 ref_clk_mpllb_div = REG_FIELD_GET(C20_REF_CLK_MPLLB_DIV_MASK, pll_state->mplla[6]); in intel_c20pll_calc_port_clock()
2447 case 162000: /* 1.62 Gbps DP1.4 */ in intel_c20_get_dp_rate()
2449 case 270000: /* 2.7 Gbps DP1.4 */ in intel_c20_get_dp_rate()
2451 case 540000: /* 5.4 Gbps DP 1.4 */ in intel_c20_get_dp_rate()
2453 case 810000: /* 8.1 Gbps DP1.4 */ in intel_c20_get_dp_rate()
2455 case 216000: /* 2.16 Gbps eDP */ in intel_c20_get_dp_rate()
2457 case 243000: /* 2.43 Gbps eDP */ in intel_c20_get_dp_rate()
2459 case 324000: /* 3.24 Gbps eDP */ in intel_c20_get_dp_rate()
2460 return 6; in intel_c20_get_dp_rate()
2461 case 432000: /* 4.32 Gbps eDP */ in intel_c20_get_dp_rate()
2463 case 1000000: /* 10 Gbps DP2.0 */ in intel_c20_get_dp_rate()
2465 case 1350000: /* 13.5 Gbps DP2.0 */ in intel_c20_get_dp_rate()
2467 case 2000000: /* 20 Gbps DP2.0 */ in intel_c20_get_dp_rate()
2469 case 648000: /* 6.48 Gbps eDP*/ in intel_c20_get_dp_rate()
2471 case 675000: /* 6.75 Gbps eDP*/ in intel_c20_get_dp_rate()
2485 case 300000: /* 3 Gbps */ in intel_c20_get_hdmi_rate()
2486 case 600000: /* 6 Gbps */ in intel_c20_get_hdmi_rate()
2487 case 1200000: /* 12 Gbps */ in intel_c20_get_hdmi_rate()
2489 case 800000: /* 8 Gbps */ in intel_c20_get_hdmi_rate()
2491 case 1000000: /* 10 Gbps */ in intel_c20_get_hdmi_rate()
2511 case 300000: /* 3 Gbps */ in is_hdmi_frl()
2512 case 600000: /* 6 Gbps */ in is_hdmi_frl()
2513 case 800000: /* 8 Gbps */ in is_hdmi_frl()
2514 case 1000000: /* 10 Gbps */ in is_hdmi_frl()
2515 case 1200000: /* 12 Gbps */ in is_hdmi_frl()
2625 /* 5. For DP or 6. For HDMI */ in intel_c20_pll_program()
2628 BIT(6) | PHY_C20_CUSTOM_SERDES_MASK, in intel_c20_pll_program()
2629 BIT(6) | PHY_C20_CUSTOM_SERDES(intel_c20_get_dp_rate(clock)), in intel_c20_pll_program()
2970 * 6. Program the enabled and disabled owned PHY lane in intel_cx0pll_enable()
3095 * 6. Follow the Display Voltage Frequency Switching Sequence After in intel_mtl_tbt_pll_enable()
3168 * 6. Follow the Display Voltage Frequency Switching Sequence After in intel_cx0pll_disable()
3215 /* 6. Program DDI_CLK_VALFREQ to 0. */ in intel_mtl_tbt_pll_disable()