| /linux-6.12.1/arch/alpha/lib/ |
| D | ev6-memset.S | 23 * A future enhancement might be to put in a byte store loop for really
25 * a win in the kernel would depend upon the contextual usage.
41 .align 5
48 * undertake a major re-write to interleave the constant materialization
64 inswl $17,4,$5 # U : 0000chch00000000
69 or $2,$5,$2 # E : chchchch00000000
70 bic $1,7,$1 # E : fit within a single quadword?
79 * Target address is misaligned, and won't fit within a quadword
82 bis $16,$16,$5 # E : Save the address
92 stq_u $1,0($5) # L : Store result
[all …]
|
| /linux-6.12.1/tools/testing/selftests/mm/ |
| D | mremap_dontunmap.c | 40 // Try a simple operation for to "test" for kernel support this prevents
97 unsigned long num_pages = 5; in mremap_dontunmap_simple()
104 memset(source_mapping, 'a', num_pages * page_size); in mremap_dontunmap_simple()
113 // the dest_mapping contains a's. in mremap_dontunmap_simple()
115 (dest_mapping, num_pages * page_size, 'a') != 0, in mremap_dontunmap_simple()
128 // This test validates that MREMAP_DONTUNMAP on a shared mapping works as expected.
131 unsigned long num_pages = 5; in mremap_dontunmap_simple_shmem()
146 memset(source_mapping, 'a', num_pages * page_size); in mremap_dontunmap_simple_shmem()
162 // the dest_mapping contains a's. in mremap_dontunmap_simple_shmem()
164 (dest_mapping, num_pages * page_size, 'a') != 0, in mremap_dontunmap_simple_shmem()
[all …]
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| /linux-6.12.1/tools/perf/pmu-events/arch/x86/alderlaken/ |
| D | pipeline.json | 4 "Counter": "0,1,2,3,4,5",
8 … in which the instruction pointer (IP) of the processor is resteered due to a branch instruction a…
13 "Counter": "0,1,2,3,4,5",
23 "Counter": "0,1,2,3,4,5",
32 "Counter": "0,1,2,3,4,5",
41 "Counter": "0,1,2,3,4,5",
50 "Counter": "0,1,2,3,4,5",
59 "Counter": "0,1,2,3,4,5",
68 "Counter": "0,1,2,3,4,5",
78 "Counter": "0,1,2,3,4,5",
[all …]
|
| /linux-6.12.1/Documentation/input/devices/ |
| D | elantech.rst | 22 5. Hardware version 2
57 combine a status packet with multiple head or motion packets. Hardware version
58 4 allows tracking up to 5 fingers.
60 Some Hardware version 3 and version 4 also have a trackpoint which uses a
67 Note that a mouse button is also associated with either the touchpad or the
68 trackpoint when a trackpoint is available. Disabling the Touchpad in xorg
101 Currently a value of "1" will turn on some basic debugging and a value of
107 generate quite a lot of data!
118 calculating a parity bit for the last 3 bytes of each packet. The driver
175 By echoing a hexadecimal value to a register it contents can be altered.
[all …]
|
| D | alps.rst | 8 ALPS touchpads, called versions 1, 2, 3, 4, 5, 6, 7 and 8.
11 integrated into a variety of laptops and netbooks. These new touchpads
23 (Compatibility ID) definition as a way to uniquely identify the
24 different ALPS variants but there did not appear to be a 1:1 mapping.
32 E8-E6-E6-E6-E9. An ALPS touchpad should respond with either 00-00-0A or
45 The new ALPS touchpads have an E7 signature of 73-03-50 or 73-03-0A but
51 Protocol versions 3 and 4 have a command mode that is used to read and write
52 one-byte device registers in a 16-bit address space. The command sequence
54 with 88-07 followed by a third byte. This third byte can be used to determine
59 While in command mode, register addresses can be set by first sending a
[all …]
|
| /linux-6.12.1/tools/perf/pmu-events/arch/x86/alderlake/ |
| D | pipeline.json | 4 "Counter": "0,1,2,3,4,5,6,7",
15 "Counter": "0,1,2,3,4,5,6,7",
26 "Counter": "0,1,2,3,4,5,6,7",
37 "Counter": "0,1,2,3,4,5,6,7",
47 "Counter": "0,1,2,3,4,5,6,7",
57 … "BriefDescription": "Number of occurrences where a microcode assist is invoked by hardware.",
58 "Counter": "0,1,2,3,4,5,6,7",
61 …"PublicDescription": "Counts the number of occurrences where a microcode assist is invoked by hard…
68 "Counter": "0,1,2,3,4,5",
72 … in which the instruction pointer (IP) of the processor is resteered due to a branch instruction a…
[all …]
|
| /linux-6.12.1/tools/perf/pmu-events/arch/x86/graniterapids/ |
| D | pipeline.json | 4 "Counter": "0,1,2,3,4,5,6,7",
14 "Counter": "0,1,2,3,4,5,6,7",
22 … "BriefDescription": "Number of occurrences where a microcode assist is invoked by hardware.",
23 "Counter": "0,1,2,3,4,5,6,7",
26 …"PublicDescription": "Counts the number of occurrences where a microcode assist is invoked by hard…
32 "Counter": "0,1,2,3,4,5,6,7",
41 "Counter": "0,1,2,3,4,5,6,7",
51 "Counter": "0,1,2,3,4,5,6,7",
61 "Counter": "0,1,2,3,4,5,6,7",
71 "Counter": "0,1,2,3,4,5,6,7",
[all …]
|
| D | frontend.json | 7 …s resteered when it finds a branch instruction in a fetch line. This is called Unknown Branch whic…
16 …to the number of prefixes in a 16B-line. This may result in a three-cycle penalty for each LCP (Le…
33 …a Uop-cache that holds translations of previously fetched instructions that were decoded by the le…
39 "Counter": "0,1,2,3,4,5,6,7",
51 "Counter": "0,1,2,3,4,5,6,7",
62 "BriefDescription": "Retired Instructions who experienced a critical DSB miss.",
63 "Counter": "0,1,2,3,4,5,6,7",
69 …erienced a critical DSB (Decode stream buffer i.e. the decoded instruction-cache) miss. Critical m…
75 "Counter": "0,1,2,3,4,5,6,7",
87 "Counter": "0,1,2,3,4,5,6,7",
[all …]
|
| /linux-6.12.1/tools/perf/pmu-events/arch/x86/meteorlake/ |
| D | pipeline.json | 4 "Counter": "0,1,2,3,4,5,6,7",
14 "Counter": "0,1,2,3,4,5,6,7",
25 "Counter": "0,1,2,3,4,5,6,7",
34 … "BriefDescription": "Number of occurrences where a microcode assist is invoked by hardware.",
35 "Counter": "0,1,2,3,4,5,6,7",
38 …"PublicDescription": "Counts the number of occurrences where a microcode assist is invoked by hard…
45 "Counter": "0,1,2,3,4,5,6,7",
48 … in which the instruction pointer (IP) of the processor is resteered due to a branch instruction a…
54 "Counter": "0,1,2,3,4,5,6,7",
64 "Counter": "0,1,2,3,4,5,6,7",
[all …]
|
| D | frontend.json | 4 "Counter": "0,1,2,3,4,5,6,7",
7 …the Branch Target Buffer (BTB) prediction or lack thereof, was corrected by a later branch predict…
17 …s resteered when it finds a branch instruction in a fetch line. This is called Unknown Branch whic…
27 …to the number of prefixes in a 16B-line. This may result in a three-cycle penalty for each LCP (Le…
46 …a Uop-cache that holds translations of previously fetched instructions that were decoded by the le…
53 "Counter": "0,1,2,3,4,5,6,7",
66 "Counter": "0,1,2,3,4,5,6,7",
78 "BriefDescription": "Retired Instructions who experienced a critical DSB miss.",
79 "Counter": "0,1,2,3,4,5,6,7",
85 …erienced a critical DSB (Decode stream buffer i.e. the decoded instruction-cache) miss. Critical m…
[all …]
|
| /linux-6.12.1/tools/perf/pmu-events/arch/x86/tigerlake/ |
| D | pipeline.json | 4 "Counter": "0,1,2,3,4,5,6,7",
13 … "BriefDescription": "Number of occurrences where a microcode assist is invoked by hardware.",
14 "Counter": "0,1,2,3,4,5,6,7",
17 …"PublicDescription": "Counts the number of occurrences where a microcode assist is invoked by hard…
23 "Counter": "0,1,2,3,4,5,6,7",
32 "Counter": "0,1,2,3,4,5,6,7",
42 "Counter": "0,1,2,3,4,5,6,7",
52 "Counter": "0,1,2,3,4,5,6,7",
62 "Counter": "0,1,2,3,4,5,6,7",
72 "Counter": "0,1,2,3,4,5,6,7",
[all …]
|
| /linux-6.12.1/tools/perf/pmu-events/arch/x86/icelake/ |
| D | pipeline.json | 4 "Counter": "0,1,2,3,4,5,6,7",
13 … "BriefDescription": "Number of occurrences where a microcode assist is invoked by hardware.",
14 "Counter": "0,1,2,3,4,5,6,7",
17 …"PublicDescription": "Counts the number of occurrences where a microcode assist is invoked by hard…
23 "Counter": "0,1,2,3,4,5,6,7",
32 "Counter": "0,1,2,3,4,5,6,7",
42 "Counter": "0,1,2,3,4,5,6,7",
52 "Counter": "0,1,2,3,4,5,6,7",
62 "Counter": "0,1,2,3,4,5,6,7",
72 "Counter": "0,1,2,3,4,5,6,7",
[all …]
|
| /linux-6.12.1/tools/perf/pmu-events/arch/x86/rocketlake/ |
| D | pipeline.json | 4 "Counter": "0,1,2,3,4,5,6,7",
13 … "BriefDescription": "Number of occurrences where a microcode assist is invoked by hardware.",
14 "Counter": "0,1,2,3,4,5,6,7",
17 …"PublicDescription": "Counts the number of occurrences where a microcode assist is invoked by hard…
23 "Counter": "0,1,2,3,4,5,6,7",
32 "Counter": "0,1,2,3,4,5,6,7",
42 "Counter": "0,1,2,3,4,5,6,7",
52 "Counter": "0,1,2,3,4,5,6,7",
62 "Counter": "0,1,2,3,4,5,6,7",
72 "Counter": "0,1,2,3,4,5,6,7",
[all …]
|
| /linux-6.12.1/tools/perf/pmu-events/arch/x86/icelakex/ |
| D | pipeline.json | 4 "Counter": "0,1,2,3,4,5,6,7",
13 … "BriefDescription": "Number of occurrences where a microcode assist is invoked by hardware.",
14 "Counter": "0,1,2,3,4,5,6,7",
17 …"PublicDescription": "Counts the number of occurrences where a microcode assist is invoked by hard…
23 "Counter": "0,1,2,3,4,5,6,7",
32 "Counter": "0,1,2,3,4,5,6,7",
42 "Counter": "0,1,2,3,4,5,6,7",
52 "Counter": "0,1,2,3,4,5,6,7",
62 "Counter": "0,1,2,3,4,5,6,7",
72 "Counter": "0,1,2,3,4,5,6,7",
[all …]
|
| /linux-6.12.1/tools/perf/pmu-events/arch/x86/emeraldrapids/ |
| D | pipeline.json | 4 "Counter": "0,1,2,3,4,5,6,7",
14 "Counter": "0,1,2,3,4,5,6,7",
24 "Counter": "0,1,2,3,4,5,6,7",
34 "Counter": "0,1,2,3,4,5,6,7",
43 "Counter": "0,1,2,3,4,5,6,7",
52 … "BriefDescription": "Number of occurrences where a microcode assist is invoked by hardware.",
53 "Counter": "0,1,2,3,4,5,6,7",
56 …"PublicDescription": "Counts the number of occurrences where a microcode assist is invoked by hard…
62 "Counter": "0,1,2,3,4,5,6,7",
71 "Counter": "0,1,2,3,4,5,6,7",
[all …]
|
| /linux-6.12.1/tools/perf/pmu-events/arch/x86/sapphirerapids/ |
| D | pipeline.json | 4 "Counter": "0,1,2,3,4,5,6,7",
14 "Counter": "0,1,2,3,4,5,6,7",
24 "Counter": "0,1,2,3,4,5,6,7",
34 "Counter": "0,1,2,3,4,5,6,7",
43 "Counter": "0,1,2,3,4,5,6,7",
52 … "BriefDescription": "Number of occurrences where a microcode assist is invoked by hardware.",
53 "Counter": "0,1,2,3,4,5,6,7",
56 …"PublicDescription": "Counts the number of occurrences where a microcode assist is invoked by hard…
62 "Counter": "0,1,2,3,4,5,6,7",
71 "Counter": "0,1,2,3,4,5,6,7",
[all …]
|
| /linux-6.12.1/arch/powerpc/crypto/ |
| D | aes-tab-4k.S | 10 * crypto/aes_generic.c and are designed to be simply accessed by a combination
11 * of rlwimi/lwz instructions with a minimum of table registers (usually only
19 * This is a quite good tradeoff for low power devices (e.g. routers) without
25 #define R(a, b, c, d) \ argument
26 0x##a##b##c##d, 0x##d##a##b##c, 0x##c##d##a##b, 0x##b##c##d##a
40 .long R(4d, ab, ab, e6), R(ec, 76, 76, 9a)
46 .long R(5f, a2, a2, fd), R(45, af, af, ea)
48 .long R(e4, 72, 72, 96), R(9b, c0, c0, 5b)
50 .long R(3d, 93, 93, ae), R(4c, 26, 26, 6a)
51 .long R(6c, 36, 36, 5a), R(7e, 3f, 3f, 41)
[all …]
|
| /linux-6.12.1/tools/perf/pmu-events/arch/x86/grandridge/ |
| D | virtual-memory.json | 3 …s but second level hits due to a demand load that did not start a page walk. Accounts for all page…
4 "Counter": "0,1,2,3,4,5,6,7",
12 "Counter": "0,1,2,3,4,5,6,7",
19 …"BriefDescription": "Counts the number of page walks completed due to load DTLB misses to a 2M or …
20 "Counter": "0,1,2,3,4,5,6,7",
28 …"BriefDescription": "Counts the number of page walks completed due to load DTLB misses to a 4K pag…
29 "Counter": "0,1,2,3,4,5,6,7",
38 "Counter": "0,1,2,3,4,5,6,7",
41 …ge walks outstanding for Loads (demand or SW prefetch) in PMH every cycle. A PMH page walk is out…
46 …nd level hits due to stores that did not start a page walk. Accounts for all pages sizes. Will res…
[all …]
|
| D | pipeline.json | 4 "Counter": "0,1,2,3,4,5,6,7",
13 "Counter": "0,1,2,3,4,5,6,7",
16 … in which the instruction pointer (IP) of the processor is resteered due to a branch instruction a…
21 "Counter": "0,1,2,3,4,5,6,7",
29 "Counter": "0,1,2,3,4,5,6,7",
37 "Counter": "0,1,2,3,4,5,6,7",
45 "Counter": "0,1,2,3,4,5,6,7",
53 "Counter": "0,1,2,3,4,5,6,7",
61 "Counter": "0,1,2,3,4,5,6,7",
70 "Counter": "0,1,2,3,4,5,6,7",
[all …]
|
| /linux-6.12.1/tools/perf/pmu-events/arch/x86/sierraforest/ |
| D | virtual-memory.json | 3 …s but second level hits due to a demand load that did not start a page walk. Accounts for all page…
4 "Counter": "0,1,2,3,4,5,6,7",
12 "Counter": "0,1,2,3,4,5,6,7",
19 …"BriefDescription": "Counts the number of page walks completed due to load DTLB misses to a 2M or …
20 "Counter": "0,1,2,3,4,5,6,7",
28 …"BriefDescription": "Counts the number of page walks completed due to load DTLB misses to a 4K pag…
29 "Counter": "0,1,2,3,4,5,6,7",
38 "Counter": "0,1,2,3,4,5,6,7",
41 …ge walks outstanding for Loads (demand or SW prefetch) in PMH every cycle. A PMH page walk is out…
46 …nd level hits due to stores that did not start a page walk. Accounts for all pages sizes. Will res…
[all …]
|
| D | pipeline.json | 4 "Counter": "0,1,2,3,4,5,6,7",
13 "Counter": "0,1,2,3,4,5,6,7",
16 … in which the instruction pointer (IP) of the processor is resteered due to a branch instruction a…
21 "Counter": "0,1,2,3,4,5,6,7",
29 "Counter": "0,1,2,3,4,5,6,7",
37 "Counter": "0,1,2,3,4,5,6,7",
45 "Counter": "0,1,2,3,4,5,6,7",
53 "Counter": "0,1,2,3,4,5,6,7",
61 "Counter": "0,1,2,3,4,5,6,7",
70 "Counter": "0,1,2,3,4,5,6,7",
[all …]
|
| /linux-6.12.1/Documentation/admin-guide/perf/ |
| D | hisi-pmu.rst | 26 Each L3C, HHA and DDRC is registered as a separate PMU with perf. The PMU
37 The driver also provides a "cpumask" sysfs attribute, which shows the CPU core
52 $# perf stat -a -e hisi_sccl3_l3c0/rd_hit_cpipe/ sleep 5
53 $# perf stat -a -e hisi_sccl3_l3c0/config=0x02/ sleep 5
59 specified as a bitmap::
61 $# perf stat -a -e hisi_sccl3_l3c0/config=0x02,tt_core=0x3/ sleep 5
71 $# perf stat -a -e hisi_sccl3_l3c0/config=0x02,tt_req=0x4/ sleep 5
75 3. Datasrc allows the user to check where the data comes from. It is 5 bits.
78 - 5'b00001: comes from L3C in this die;
79 - 5'b01000: comes from L3C in the cross-die;
[all …]
|
| /linux-6.12.1/drivers/net/ipa/ |
| D | ipa_reg.h | 19 * Device Tree. Each register has a specified offset within that space,
21 * has a unique identifer, taken from the ipa_reg_id enumerated type.
24 * Certain "parameterized" register types are duplicated for a number of
28 * ID multiplied and a "stride" value for the register. Similarly, some
30 * this case, the stride is multiplied by a member of the gsi_ee_id
35 * (for parameterized registers) a non-zero stride value. Not all versions
36 * of IPA define all registers. The offset for a register is returned by
41 * such a register has a unique identifier (from an enumerated type).
42 * The position and width of the fields in a register are defined by
45 * argument. To encode a value to be represented in a register field,
[all …]
|
| /linux-6.12.1/arch/m68k/fpsp040/ |
| D | tbldo.S | 10 | index with a 10-bit index, with the first
54 .long smovcr |$00-5 fmovecr all
63 .long serror |$01-5 fint ERROR
72 .long serror |$02-5 fsinh ERROR
81 .long serror |$03-5 fintrz ERROR
90 .long serror |$04-5 ERROR - illegal extension
99 .long serror |$05-5 ERROR - illegal extension
108 .long serror |$06-5 flognp1 ERROR
117 .long serror |$07-5 ERROR - illegal extension
126 .long serror |$08-5 fetoxm1 ERROR
[all …]
|
| /linux-6.12.1/tools/perf/pmu-events/arch/x86/lunarlake/ |
| D | pipeline.json | 4 "Counter": "0,1,2,3,4,5,6,7",
8 … in which the instruction pointer (IP) of the processor is resteered due to a branch instruction a…
14 "Counter": "0,1,2,3,4,5,6,7,8,9",
24 "Counter": "0,1,2,3,4,5,6,7",
28 …ranch and on the execution path through which execution reached this IP. A branch misprediction…
34 "Counter": "0,1,2,3,4,5,6,7,8,9",
38 …ll the retired branch instructions that were mispredicted by the processor. A branch misprediction…
51 "BriefDescription": "Core cycles when the core is not in a halt state.",
54 …a halt state. The core enters the halt state when it is running the HLT instruction. This event is…
61 "Counter": "0,1,2,3,4,5,6,7",
[all …]
|