Lines Matching +full:5 +full:a
23 * A future enhancement might be to put in a byte store loop for really
25 * a win in the kernel would depend upon the contextual usage.
41 .align 5
48 * undertake a major re-write to interleave the constant materialization
64 inswl $17,4,$5 # U : 0000chch00000000
69 or $2,$5,$2 # E : chchchch00000000
70 bic $1,7,$1 # E : fit within a single quadword?
79 * Target address is misaligned, and won't fit within a quadword
82 bis $16,$16,$5 # E : Save the address
92 stq_u $1,0($5) # L : Store result
105 bis $16,$16,$5 # E : Save dest address
110 * Lifted a bunch of code from clear_user.S
113 * $5 A copy of $16
126 * through unrolled loop. Do a quad at a time to get us 0mod64
136 stq $17, 0($5) # L :
139 addq $5, 8, $4 # E : Initial wh64 address (filler instruction)
143 addq $5, 8, $5 # E : Inc address
149 * $5 - target address (aligned 0mod64)
152 * we know that we'll be taking a minimum of one trip through
153 * CWG Section 3.7.6: do not expect a sustained store rate of > 1/cycle
163 stq $17, 0($5) # L :
166 addq $5, 128, $4 # E : speculative target of next wh64
167 stq $17, 8($5) # L :
168 stq $17, 16($5) # L :
169 addq $5, 64, $7 # E : Fallback address for wh64 (== next trip addr)
171 stq $17, 24($5) # L :
172 stq $17, 32($5) # L :
176 stq $17, 40($5) # L :
177 stq $17, 48($5) # L :
181 stq $17, 56($5) # L :
182 addq $5, 64, $5 # E :
197 stq $17,0($5) # L :
199 addq $5,8,$5 # E : Inc address
208 ldq $7,0($5) # L :
213 stq $1,0($5) # L : And back to memory
251 bic $1,7,$1 # E : fit within a single quadword
257 * Target address is misaligned, and won't fit within a quadword
260 bis $16,$16,$5 # E : Save the address
270 stq_u $1,0($5) # L : Store result
283 bis $16,$16,$5 # E : Save dest address
288 * Lifted a bunch of code from clear_user.S
291 * $5 A copy of $16
304 * through unrolled loop. Do a quad at a time to get us 0mod64
314 stq $17, 0($5) # L :
317 addq $5, 8, $4 # E : Initial wh64 address (filler instruction)
321 addq $5, 8, $5 # E : Inc address
327 * $5 - target address (aligned 0mod64)
330 * we know that we'll be taking a minimum of one trip through
331 * CWG Section 3.7.6: do not expect a sustained store rate of > 1/cycle
341 stq $17, 0($5) # L :
344 addq $5, 128, $4 # E : speculative target of next wh64
345 stq $17, 8($5) # L :
346 stq $17, 16($5) # L :
347 addq $5, 64, $7 # E : Fallback address for wh64 (== next trip addr)
349 stq $17, 24($5) # L :
350 stq $17, 32($5) # L :
354 stq $17, 40($5) # L :
355 stq $17, 48($5) # L :
359 stq $17, 56($5) # L :
360 addq $5, 64, $5 # E :
375 stq $17,0($5) # L :
377 addq $5,8,$5 # E : Inc address
386 ldq $7,0($5) # L :
391 stq $1,0($5) # L : And back to memory
414 * This is a replicant of the __constant_c_memset code, rescheduled
417 .align 5
424 inswl $17,0,$5 # U : 000000000000c1c2
434 or $2,$5,$2 # E : 00000000c1c2c1c2
436 bic $1,7,$1 # E : fit within a single quadword
445 * Target address is misaligned, and won't fit within a quadword
448 bis $16,$16,$5 # E : Save the address
458 stq_u $1,0($5) # L : Store result
471 bis $16,$16,$5 # E : Save dest address
476 * Lifted a bunch of code from clear_user.S
479 * $5 A copy of $16
492 * through unrolled loop. Do a quad at a time to get us 0mod64
502 stq $17, 0($5) # L :
505 addq $5, 8, $4 # E : Initial wh64 address (filler instruction)
509 addq $5, 8, $5 # E : Inc address
515 * $5 - target address (aligned 0mod64)
518 * we know that we'll be taking a minimum of one trip through
519 * CWG Section 3.7.6: do not expect a sustained store rate of > 1/cycle
529 stq $17, 0($5) # L :
532 addq $5, 128, $4 # E : speculative target of next wh64
533 stq $17, 8($5) # L :
534 stq $17, 16($5) # L :
535 addq $5, 64, $7 # E : Fallback address for wh64 (== next trip addr)
537 stq $17, 24($5) # L :
538 stq $17, 32($5) # L :
542 stq $17, 40($5) # L :
543 stq $17, 48($5) # L :
547 stq $17, 56($5) # L :
548 addq $5, 64, $5 # E :
563 stq $17,0($5) # L :
565 addq $5,8,$5 # E : Inc address
574 ldq $7,0($5) # L :
579 stq $1,0($5) # L : And back to memory