x86/lunarlake/pipeline.json

4         "Counter": "0,1,2,3,4,5,6,7",
8 … in which the instruction pointer (IP) of the processor is resteered due to a branch instruction a…
14         "Counter": "0,1,2,3,4,5,6,7,8,9",
24         "Counter": "0,1,2,3,4,5,6,7",
28 …ranch and on the execution path through which execution reached this IP.    A branch misprediction…
34         "Counter": "0,1,2,3,4,5,6,7,8,9",
38 …ll the retired branch instructions that were mispredicted by the processor. A branch misprediction…
51         "BriefDescription": "Core cycles when the core is not in a halt state.",
54 …a halt state. The core enters the halt state when it is running the HLT instruction. This event is…
61         "Counter": "0,1,2,3,4,5,6,7",
69         "Counter": "0,1,2,3,4,5,6,7,8,9",
72 …a halt state. The thread enters the halt state when it is running the HLT instruction. The core fr…
88 …a halt state. The core enters the halt state when it is running the HLT instruction or the MWAIT i…
95         "Counter": "0,1,2,3,4,5,6,7",
98 …a halt state. The core enters the halt state when it is running the HLT instruction. This event is…
105         "Counter": "0,1,2,3,4,5,6,7,8,9",
108 …a halt state. The core enters the halt state when it is running the HLT instruction or the MWAIT i…
122         "BriefDescription": "Core cycles when the thread is not in a halt state.",
125 …a halt state. The thread enters the halt state when it is running the HLT instruction. This event …
132         "Counter": "0,1,2,3,4,5,6,7",
140         "Counter": "0,1,2,3,4,5,6,7,8,9",
143 …a halt state. The thread enters the halt state when it is running the HLT instruction. The core fr…
161 …ANY is counted by a designated fixed counter freeing up programmable counters to count other event…
168         "Counter": "0,1,2,3,4,5,6,7",
177         "Counter": "0,1,2,3,4,5,6,7,8,9",
181 …ANY is counted by a designated fixed counter freeing up programmable counters to count other event…
186 …"BriefDescription": "Counts the number of occurrences a retired load gets blocked because its addr…
187         "Counter": "0,1,2,3,4,5,6,7",
196 …"BriefDescription": "Loads blocked due to overlapping with a preceding store that cannot be forwar…
197         "Counter": "0,1,2,3,4,5,6,7,8,9",
200 … prevented for a load operation. The most common case is a load blocked due to the address of memo…
207         "Counter": "0,1,2,3,4,5,6,7",
217         "Counter": "0,1,2,3,4,5,6,7,8,9",
226 …s event counts a subset of the Topdown Slots event that were not consumed by the back-end pipeline…
227         "Counter": "0,1,2,3,4,5,6,7,8,9",
230 …s event counts a subset of the Topdown Slots event that were not consumed by the back-end pipeline…
239 …top-level metrics of the TMA method. This architectural event is counted on a designated fixed cou…
246         "Counter": "0,1,2,3,4,5,6,7,8,9",
255 …ot consumed by the backend because allocation is stalled due to a mispredicted jump or a machine c…
256         "Counter": "0,1,2,3,4,5,6,7",
263 …ot consumed by the backend because allocation is stalled due to a mispredicted jump or a machine c…
264         "Counter": "0,1,2,3,4,5,6,7",
272         "Counter": "0,1,2,3,4,5,6,7",
281         "Counter": "0,1,2,3,4,5,6,7",
298         "Counter": "0,1,2,3,4,5,6,7",
316         "Counter": "0,1,2,3,4,5,6,7",
325 …"BriefDescription": "This event counts a subset of the Topdown Slots event that are utilized by op…
326         "Counter": "0,1,2,3,4,5,6,7,8,9",
329 …"PublicDescription": "This event counts a subset of the Topdown Slots event that are utilized by o…