x86/alderlaken/pipeline.json

4         "Counter": "0,1,2,3,4,5",
8 … in which the instruction pointer (IP) of the processor is resteered due to a branch instruction a…
13         "Counter": "0,1,2,3,4,5",
23         "Counter": "0,1,2,3,4,5",
32         "Counter": "0,1,2,3,4,5",
41         "Counter": "0,1,2,3,4,5",
50         "Counter": "0,1,2,3,4,5",
59         "Counter": "0,1,2,3,4,5",
68         "Counter": "0,1,2,3,4,5",
78         "Counter": "0,1,2,3,4,5",
88         "Counter": "0,1,2,3,4,5",
97         "Counter": "0,1,2,3,4,5",
106         "Counter": "0,1,2,3,4,5",
115         "Counter": "0,1,2,3,4,5",
125         "Counter": "0,1,2,3,4,5",
134         "Counter": "0,1,2,3,4,5",
144         "Counter": "0,1,2,3,4,5",
154         "Counter": "0,1,2,3,4,5",
158 …ranch and on the execution path through which execution reached this IP.    A branch misprediction…
163         "Counter": "0,1,2,3,4,5",
172         "Counter": "0,1,2,3,4,5",
181         "Counter": "0,1,2,3,4,5",
190         "Counter": "0,1,2,3,4,5",
199         "Counter": "0,1,2,3,4,5",
209         "Counter": "0,1,2,3,4,5",
219         "Counter": "0,1,2,3,4,5",
228         "Counter": "0,1,2,3,4,5",
238         "Counter": "0,1,2,3,4,5",
247         "Counter": "0,1,2,3,4,5",
259 …a halt state. The core enters the halt state when it is running the HLT instruction. The core freq…
265         "Counter": "0,1,2,3,4,5",
268 …a halt state. The core enters the halt state when it is running the HLT instruction. The core freq…
275 …a halt state. The core enters the halt state when it is running the HLT instruction. This event is…
281         "Counter": "0,1,2,3,4,5",
284 …a halt state. The core enters the halt state when it is running the HLT instruction. This event is…
292 …a halt state.  The core enters the halt state when it is running the HLT instruction. The core fre…
298         "Counter": "0,1,2,3,4,5",
301 …a halt state.  The core enters the halt state when it is running the HLT instruction. The core fre…
315         "Counter": "0,1,2,3,4,5",
319 … hardware interrupts, traps, and inside interrupt handlers. This event uses a programmable general…
324         "Counter": "0,1,2,3,4,5",
334         "Counter": "0,1,2,3,4,5",
343         "Counter": "0,1,2,3,4,5",
352         "Counter": "0,1,2,3,4,5",
360         "Counter": "0,1,2,3,4,5",
367 …ts the number of machine clears due to a page fault.  Counts both I-Side and D-Side (Loads/Stores)…
368         "Counter": "0,1,2,3,4,5",
376         "Counter": "0,1,2,3,4,5",
383 …ine clears due to program modifying data (self modifying code) within 1K of a recently fetched cod…
384         "Counter": "0,1,2,3,4,5",
392         "Counter": "0,1,2,3,4,5",
401 …sumed by the backend due to a micro-sequencer (MS) scoreboard, which stalls the front-end from iss…
402         "Counter": "0,1,2,3,4,5",
405 …sumed by the backend due to a micro-sequencer (MS) scoreboard, which stalls the front-end from iss…
410 …ot consumed by the backend because allocation is stalled due to a mispredicted jump or a machine c…
411         "Counter": "0,1,2,3,4,5",
414 …ot consumed by the backend because allocation is stalled due to a mispredicted jump or a machine c…
419         "Counter": "0,1,2,3,4,5",
426 … that were not consumed by the backend because allocation is stalled due to a machine clear (nuke)…
427         "Counter": "0,1,2,3,4,5",
435         "Counter": "0,1,2,3,4,5",
442 …ber of issue slots every cycle that were not consumed by the backend due to a machine clear (nuke)…
443         "Counter": "0,1,2,3,4,5",
451         "Counter": "0,1,2,3,4,5",
458         "Counter": "0,1,2,3,4,5",
465 … were not consumed by the backend due to memory reservation stalls in which a scheduler is not abl…
466         "Counter": "0,1,2,3,4,5",
474         "Counter": "0,1,2,3,4,5",
482         "Counter": "0,1,2,3,4,5",
490         "Counter": "0,1,2,3,4,5",
498         "Counter": "0,1,2,3,4,5",
506         "Counter": "0,1,2,3,4,5",
513         "Counter": "0,1,2,3,4,5",
516 …the Branch Target Buffer (BTB) prediction or lack thereof, was corrected by a later branch predict…
522         "Counter": "0,1,2,3,4,5",
525 …ontend due to BTCLEARS, which occurs when the Branch Target Buffer (BTB) predicts a taken branch.",
531         "Counter": "0,1,2,3,4,5",
539         "Counter": "0,1,2,3,4,5",
547         "Counter": "0,1,2,3,4,5",
554 …r of issue slots every cycle that were not delivered by the frontend due to a latency related stal…
555         "Counter": "0,1,2,3,4,5",
563         "Counter": "0,1,2,3,4,5",
572         "Counter": "0,1,2,3,4,5",
580         "Counter": "0,1,2,3,4,5",
588         "Counter": "0,1,2,3,4,5",
596         "Counter": "0,1,2,3,4,5",
604         "Counter": "0,1,2,3,4,5",
612         "Counter": "0,1,2,3,4,5",
621         "Counter": "0,1,2,3,4,5",
631         "Counter": "0,1,2,3,4,5",