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/linux-6.12.1/include/math-emu/
Dop-4.h28 #define _FP_FRAC_DECL_4(X) _FP_W_TYPE X##_f[4] argument
31 D##_f[2] = S##_f[2], D##_f[3] = S##_f[3])
32 #define _FP_FRAC_SET_4(X,I) __FP_FRAC_SET_4(X, I) argument
33 #define _FP_FRAC_HIGH_4(X) (X##_f[3]) argument
34 #define _FP_FRAC_LOW_4(X) (X##_f[0]) argument
35 #define _FP_FRAC_WORD_4(X,w) (X##_f[w]) argument
37 #define _FP_FRAC_SLL_4(X,N) \ argument
44 for (_i = 3; _i >= _skip; --_i) \
45 X##_f[_i] = X##_f[_i-_skip]; \
48 for (_i = 3; _i > _skip; --_i) \
[all …]
/linux-6.12.1/drivers/gpu/drm/imagination/
Dpvr_rogue_fwif_sf.h65 #define ROGUE_FW_SF_GID(x) (((u32)(x) >> 12) & 0xfU) argument
67 #define ROGUE_FW_SF_PARAMNUM(x) (((u32)(x) >> 16) & 0xfU) argument
80 "Kick 3D: FWCtx 0x%08.8x @ %d, RTD 0x%08x. Partial render:%d, CSW resume:%d, prio:%d" },
82 "3D finished, HWRTData0State=%x, HWRTData1State=%x" },
83 { ROGUE_FW_LOG_CREATESFID(3, ROGUE_FW_GROUP_MAIN, 4),
84 "Kick 3D TQ: FWCtx 0x%08.8x @ %d, CSW resume:%d, prio: %d" },
86 "3D Transfer finished" },
87 { ROGUE_FW_LOG_CREATESFID(5, ROGUE_FW_GROUP_MAIN, 3),
88 "Kick Compute: FWCtx 0x%08.8x @ %d, prio: %d" },
92 … "Kick TA: FWCtx 0x%08.8x @ %d, RTD 0x%08x. First kick:%d, Last kick:%d, CSW resume:%d, prio:%d" },
[all …]
/linux-6.12.1/drivers/net/ethernet/mscc/
Docelot_rew.h13 #define REW_PORT_VLAN_CFG_PORT_TPID(x) (((x) << 16) & GENMASK(31, 16)) argument
15 #define REW_PORT_VLAN_CFG_PORT_TPID_X(x) (((x) & GENMASK(31, 16)) >> 16) argument
17 #define REW_PORT_VLAN_CFG_PORT_PCP(x) (((x) << 12) & GENMASK(14, 12)) argument
19 #define REW_PORT_VLAN_CFG_PORT_PCP_X(x) (((x) & GENMASK(14, 12)) >> 12) argument
20 #define REW_PORT_VLAN_CFG_PORT_VID(x) ((x) & GENMASK(11, 0)) argument
25 #define REW_TAG_CFG_TAG_CFG(x) (((x) << 7) & GENMASK(8, 7)) argument
27 #define REW_TAG_CFG_TAG_CFG_X(x) (((x) & GENMASK(8, 7)) >> 7) argument
28 #define REW_TAG_CFG_TAG_TPID_CFG(x) (((x) << 5) & GENMASK(6, 5)) argument
30 #define REW_TAG_CFG_TAG_TPID_CFG_X(x) (((x) & GENMASK(6, 5)) >> 5) argument
32 #define REW_TAG_CFG_TAG_PCP_CFG(x) (((x) << 2) & GENMASK(3, 2)) argument
[all …]
Docelot_qs.h20 #define XTR_VALID_BYTES(x) (4 - (((x) >> 24) & 3)) argument
24 #define QS_XTR_GRP_CFG_MODE(x) (((x) << 2) & GENMASK(3, 2)) argument
25 #define QS_XTR_GRP_CFG_MODE_M GENMASK(3, 2)
26 #define QS_XTR_GRP_CFG_MODE_X(x) (((x) & GENMASK(3, 2)) >> 2) argument
34 #define QS_XTR_CFG_DP_WM(x) (((x) << 5) & GENMASK(7, 5)) argument
36 #define QS_XTR_CFG_DP_WM_X(x) (((x) & GENMASK(7, 5)) >> 5) argument
37 #define QS_XTR_CFG_SCH_WM(x) (((x) << 2) & GENMASK(4, 2)) argument
39 #define QS_XTR_CFG_SCH_WM_X(x) (((x) & GENMASK(4, 2)) >> 2) argument
40 #define QS_XTR_CFG_OFLW_ERR_STICKY(x) ((x) & GENMASK(1, 0)) argument
45 #define QS_INJ_GRP_CFG_MODE(x) (((x) << 2) & GENMASK(3, 2)) argument
[all …]
/linux-6.12.1/arch/csky/include/asm/
Duaccess.h11 #define __put_user_asm_b(x, ptr, err) \ argument
16 " br 3f \n" \
17 "2: mov %0, %3 \n" \
18 " br 3f \n" \
23 "3: \n" \
24 : "=r"(err), "=r"(x), "=r"(ptr), "=r"(errcode) \
25 : "0"(err), "1"(x), "2"(ptr), "3"(-EFAULT) \
29 #define __put_user_asm_h(x, ptr, err) \ argument
34 " br 3f \n" \
35 "2: mov %0, %3 \n" \
[all …]
/linux-6.12.1/drivers/comedi/drivers/
Dni_tio_internal.h14 #define NITIO_AUTO_INC_REG(x) (NITIO_G0_AUTO_INC + (x)) argument
16 #define NITIO_CMD_REG(x) (NITIO_G0_CMD + (x)) argument
21 #define GI_CNT_DIR(x) (((x) & 0x3) << 5) argument
22 #define GI_CNT_DIR_MASK GI_CNT_DIR(3)
32 #define NITIO_HW_SAVE_REG(x) (NITIO_G0_HW_SAVE + (x)) argument
33 #define NITIO_SW_SAVE_REG(x) (NITIO_G0_SW_SAVE + (x)) argument
34 #define NITIO_MODE_REG(x) (NITIO_G0_MODE + (x)) argument
35 #define GI_GATING_MODE(x) (((x) & 0x3) << 0) argument
39 #define GI_FALLING_EDGE_GATING GI_GATING_MODE(3)
40 #define GI_GATING_MODE_MASK GI_GATING_MODE(3)
[all …]
Dni_stc.h44 #define NISTC_INTB_ACK_REG 3
57 #define NISTC_INTB_ACK_AO_BC_TC_TRIG_ERR BIT(3)
79 #define NISTC_AI_CMD2_STOP_PULSE BIT(3)
85 #define NISTC_AO_CMD2_END_ON_BC_TC(x) (((x) & 0x3) << 14) argument
96 #define NISTC_AO_CMD2_MUTE_B BIT(3)
116 #define NISTC_AI_CMD1_EXTMUX_CLK_PULSE BIT(3)
134 #define NISTC_AO_CMD1_LDAC1_SRC_SEL BIT(3)
140 #define NISTC_DIO_OUT_SERIAL(x) (((x) & 0xff) << 8) argument
142 #define NISTC_DIO_OUT_PARALLEL(x) ((x) & 0xff) argument
152 #define NISTC_DIO_CTRL_DIR(x) ((x) & 0xff) argument
[all …]
Dz8536.h15 #define Z8536_INT_CTRL_PB_VIS BIT(3) /* Port B Vect Inc Status */
25 #define Z8536_CFG_CTRL_PCE_CT3E BIT(4) /* Port C & C/T 3 Enable */
26 #define Z8536_CFG_CTRL_PLC BIT(3) /* Port A/B Link Control */
28 #define Z8536_CFG_CTRL_LC(x) (((x) & 0x3) << 0) /* Link Control */ argument
32 #define Z8536_CFG_CTRL_LC_CLK Z8536_CFG_CTRL_LC(3)/* 1 Clocks 2 */
33 #define Z8536_CFG_CTRL_LC_MASK Z8536_CFG_CTRL_LC(3)
41 /* Port A/B & Counter/Timer 1/2/3 Command and Status registers */
47 #define Z8536_CT_CMDSTAT_REG(x) (0x0a + (x)) argument
48 #define Z8536_CMD(x) (((x) & 0x7) << 5) argument
52 #define Z8536_CMD_CLR_IUS Z8536_CMD(3) /* Clear IUS */
[all …]
/linux-6.12.1/include/soc/mscc/
Docelot_ana.h15 #define ANA_ANAGEFIL_PID_VAL(x) (((x) << 14) & GENMASK(18, 14)) argument
17 #define ANA_ANAGEFIL_PID_VAL_X(x) (((x) & GENMASK(18, 14)) >> 14) argument
19 #define ANA_ANAGEFIL_VID_VAL(x) ((x) & GENMASK(12, 0)) argument
24 #define ANA_STORMLIMIT_CFG_STORM_RATE(x) (((x) << 3) & GENMASK(6, 3)) argument
25 #define ANA_STORMLIMIT_CFG_STORM_RATE_M GENMASK(6, 3)
26 #define ANA_STORMLIMIT_CFG_STORM_RATE_X(x) (((x) & GENMASK(6, 3)) >> 3) argument
28 #define ANA_STORMLIMIT_CFG_STORM_MODE(x) ((x) & GENMASK(1, 0)) argument
32 #define ANA_AUTOAGE_AGE_PERIOD(x) (((x) << 1) & GENMASK(20, 1)) argument
34 #define ANA_AUTOAGE_AGE_PERIOD_X(x) (((x) & GENMASK(20, 1)) >> 1) argument
40 #define ANA_AGENCTRL_FID_MASK(x) (((x) << 12) & GENMASK(23, 12)) argument
[all …]
Docelot_hsio.h90 #define HSIO_PLL5G_CFG0_SELBGV820(x) (((x) << 23) & GENMASK(26, 23)) argument
92 #define HSIO_PLL5G_CFG0_SELBGV820_X(x) (((x) & GENMASK(26, 23)) >> 23) argument
93 #define HSIO_PLL5G_CFG0_LOOP_BW_RES(x) (((x) << 18) & GENMASK(22, 18)) argument
95 #define HSIO_PLL5G_CFG0_LOOP_BW_RES_X(x) (((x) & GENMASK(22, 18)) >> 18) argument
96 #define HSIO_PLL5G_CFG0_SELCPI(x) (((x) << 16) & GENMASK(17, 16)) argument
98 #define HSIO_PLL5G_CFG0_SELCPI_X(x) (((x) & GENMASK(17, 16)) >> 16) argument
103 #define HSIO_PLL5G_CFG0_CPU_CLK_DIV(x) (((x) << 6) & GENMASK(11, 6)) argument
105 #define HSIO_PLL5G_CFG0_CPU_CLK_DIV_X(x) (((x) & GENMASK(11, 6)) >> 6) argument
106 #define HSIO_PLL5G_CFG0_CORE_CLK_DIV(x) ((x) & GENMASK(5, 0)) argument
114 #define HSIO_PLL5G_CFG1_RC_CTRL_DATA(x) (((x) << 6) & GENMASK(13, 6)) argument
[all …]
Docelot_qsys.h18 #define QSYS_STAT_CNT_CFG_DROP_GREEN_CNT_MODE BIT(3)
25 #define QSYS_EEE_THRES_EEE_HIGH_BYTES(x) (((x) << 8) & GENMASK(15, 8)) argument
27 #define QSYS_EEE_THRES_EEE_HIGH_BYTES_X(x) (((x) & GENMASK(15, 8)) >> 8) argument
28 #define QSYS_EEE_THRES_EEE_HIGH_FRAMES(x) ((x) & GENMASK(7, 0)) argument
33 #define QSYS_EXT_CPU_CFG_EXT_CPU_PORT(x) (((x) << 8) & GENMASK(12, 8)) argument
35 #define QSYS_EXT_CPU_CFG_EXT_CPU_PORT_X(x) (((x) & GENMASK(12, 8)) >> 8) argument
36 #define QSYS_EXT_CPU_CFG_EXT_CPUQ_MSK(x) ((x) & GENMASK(7, 0)) argument
41 #define QSYS_QMAP_SE_BASE(x) (((x) << 5) & GENMASK(12, 5)) argument
43 #define QSYS_QMAP_SE_BASE_X(x) (((x) & GENMASK(12, 5)) >> 5) argument
44 #define QSYS_QMAP_SE_IDX_SEL(x) (((x) << 2) & GENMASK(4, 2)) argument
[all …]
/linux-6.12.1/drivers/gpu/drm/radeon/
Drv6xxd.h34 # define THERMAL_PROTECTION_DIS (1 << 3)
37 # define SW_GPIO_INDEX(x) ((x) << 6) argument
38 # define SW_GPIO_INDEX_MASK (3 << 6)
51 # define SU_MCLK_USE_BCLK (1 << 3)
79 # define LEVEL0_MPLL_POST_DIV(x) ((x) << 0) argument
81 # define LEVEL0_MPLL_FB_DIV(x) ((x) << 8) argument
83 # define LEVEL0_MPLL_REF_DIV(x) ((x) << 20) argument
90 # define VID_CRT(x) ((x) << 0) argument
92 # define VID_CRTU(x) ((x) << 13) argument
94 # define SSTU(x) ((x) << 16) argument
[all …]
/linux-6.12.1/drivers/gpu/drm/amd/amdgpu/
Dcikd.h57 #define PIPEID(x) ((x) << 0) argument
58 #define MEID(x) ((x) << 2) argument
59 #define VMID(x) ((x) << 4) argument
60 #define QUEUEID(x) ((x) << 8) argument
76 # define CURSOR_24_8_UNPRE_MULT 3
80 # define CURSOR_URGENT_3_8 3
92 # define GRPH_FORMAT_AI88 3
99 # define GRPH_FORMAT_8B_ARGB2101010 3
107 # define ADDR_SURF_MACRO_TILE_ASPECT_8 3
119 # define GRPH_ENDIAN_8IN64 3
[all …]
Dnvd.h33 #define PACKET_TYPE3 3
35 #define CP_PACKET_GET_TYPE(h) (((h) >> 30) & 3)
54 /* Packet 3 types */
57 #define PACKET3_BASE_INDEX(x) ((x) << 0) argument
58 #define CE_PARTITION_BASE 3
89 #define WRITE_DATA_DST_SEL(x) ((x) << 8) argument
93 * 3 - gds
99 #define WRITE_DATA_CACHE_POLICY(x) ((x) << 25) argument
103 #define WRITE_DATA_ENGINE_SEL(x) ((x) << 30) argument
117 #define WAIT_REG_MEM_FUNCTION(x) ((x) << 0) argument
[all …]
Dsoc15d.h35 #define PACKET_TYPE3 3
37 #define CP_PACKET_GET_TYPE(h) (((h) >> 30) & 3)
59 #define PACKETJ_CONDITION_CHECK3 3
68 #define PACKETJ_TYPE3 3
80 #define CP_PACKETJ_GET_REG(x) ((x) & 0x3FFFF) argument
81 #define CP_PACKETJ_GET_RES(x) (((x) >> 18) & 0x3F) argument
82 #define CP_PACKETJ_GET_COND(x) (((x) >> 24) & 0xF) argument
83 #define CP_PACKETJ_GET_TYPE(x) (((x) >> 28) & 0xF) argument
85 /* Packet 3 types */
88 #define PACKET3_BASE_INDEX(x) ((x) << 0) argument
[all …]
Dsid.h79 #define DCCG_DISP1_SLOW_SELECT(x) ((x) << 0) argument
82 #define DCCG_DISP2_SLOW_SELECT(x) ((x) << 4) argument
89 #define SPLL_BYPASS_EN (1 << 3)
90 #define SPLL_REF_DIV(x) ((x) << 4) argument
92 #define SPLL_PDIV_A(x) ((x) << 20) argument
96 #define SCLK_MUX_SEL(x) ((x) << 0) argument
101 #define SPLL_FB_DIV(x) ((x) << 0) argument
111 # define SPLL_REFCLK_SEL(x) ((x) << 26) argument
112 # define SPLL_REFCLK_SEL_MASK (3 << 26)
116 #define CLK_S(x) ((x) << 4) argument
[all …]
Dsi_enums.h40 #define LATENCY_WATERMARK_MASK(x) ((x) << 16) argument
41 #define DC_LB_MEMORY_CONFIG(x) ((x) << 20) argument
42 #define ICON_DEGAMMA_MODE(x) (((x) & 0x3) << 8) argument
44 #define GRPH_ENDIAN_SWAP(x) (((x) & 0x3) << 0) argument
48 #define GRPH_ENDIAN_8IN64 3
49 #define GRPH_RED_CROSSBAR(x) (((x) & 0x3) << 4) argument
53 #define GRPH_RED_SEL_A 3
54 #define GRPH_GREEN_CROSSBAR(x) (((x) & 0x3) << 6) argument
58 #define GRPH_GREEN_SEL_R 3
59 #define GRPH_BLUE_CROSSBAR(x) (((x) & 0x3) << 8) argument
[all …]
/linux-6.12.1/crypto/
Dsm4.c72 static inline u32 sm4_t_non_lin_sub(u32 x) in sm4_t_non_lin_sub() argument
76 out = (u32)sbox[x & 0xff]; in sm4_t_non_lin_sub()
77 out |= (u32)sbox[(x >> 8) & 0xff] << 8; in sm4_t_non_lin_sub()
78 out |= (u32)sbox[(x >> 16) & 0xff] << 16; in sm4_t_non_lin_sub()
79 out |= (u32)sbox[(x >> 24) & 0xff] << 24; in sm4_t_non_lin_sub()
84 static inline u32 sm4_key_lin_sub(u32 x) in sm4_key_lin_sub() argument
86 return x ^ rol32(x, 13) ^ rol32(x, 23); in sm4_key_lin_sub()
89 static inline u32 sm4_enc_lin_sub(u32 x) in sm4_enc_lin_sub() argument
91 return x ^ rol32(x, 2) ^ rol32(x, 10) ^ rol32(x, 18) ^ rol32(x, 24); in sm4_enc_lin_sub()
94 static inline u32 sm4_key_sub(u32 x) in sm4_key_sub() argument
[all …]
/linux-6.12.1/lib/
Dhashtable_test.c23 DECLARE_HASHTABLE(hash2, 3); in hashtable_test_hash_init()
67 struct hashtable_test_entry a, b, *x; in hashtable_test_hash_add() local
69 DEFINE_HASHTABLE(hash, 3); in hashtable_test_hash_add()
80 hash_for_each(hash, bkt, x, node) { in hashtable_test_hash_add()
81 x->visited++; in hashtable_test_hash_add()
82 if (x->key == a.key) in hashtable_test_hash_add()
83 KUNIT_EXPECT_EQ(test, x->data, 13); in hashtable_test_hash_add()
84 else if (x->key == b.key) in hashtable_test_hash_add()
85 KUNIT_EXPECT_EQ(test, x->data, 10); in hashtable_test_hash_add()
97 struct hashtable_test_entry a, b, *x; in hashtable_test_hash_del() local
[all …]
/linux-6.12.1/sound/pci/ice1712/
Dhoontech.h30 #define ICE1712_STDSP24_0_BOX(r, x) r[0] = ((r[0] & ~3) | ((x)&3)) argument
31 #define ICE1712_STDSP24_0_DAREAR(r, x) r[0] = ((r[0] & ~4) | (((x)&1)<<2)) argument
32 #define ICE1712_STDSP24_1_CHN1(r, x) r[1] = ((r[1] & ~1) | ((x)&1)) argument
33 #define ICE1712_STDSP24_1_CHN2(r, x) r[1] = ((r[1] & ~2) | (((x)&1)<<1)) argument
34 #define ICE1712_STDSP24_1_CHN3(r, x) r[1] = ((r[1] & ~4) | (((x)&1)<<2)) argument
35 #define ICE1712_STDSP24_2_CHN4(r, x) r[2] = ((r[2] & ~1) | ((x)&1)) argument
36 #define ICE1712_STDSP24_2_MIDIIN(r, x) r[2] = ((r[2] & ~2) | (((x)&1)<<1)) argument
37 #define ICE1712_STDSP24_2_MIDI1(r, x) r[2] = ((r[2] & ~4) | (((x)&1)<<2)) argument
38 #define ICE1712_STDSP24_3_MIDI2(r, x) r[3] = ((r[3] & ~1) | ((x)&1)) argument
39 #define ICE1712_STDSP24_3_MUTE(r, x) r[3] = ((r[3] & ~2) | (((x)&1)<<1)) argument
[all …]
/linux-6.12.1/sound/soc/codecs/
Dcs42l51.h26 #define CS42L51_MK_CHIP_REV(a, b) ((a)<<3|(b))
32 #define CS42L51_POWER_CTL1_PDN_PGAA (1<<3)
39 #define CS42L51_MIC_POWER_CTL_SPEED(x) (((x)&3)<<5) argument
40 #define CS42L51_QSM_MODE 3
45 #define CS42L51_MIC_POWER_CTL_PDN_MICB (1<<3)
53 #define CS42L51_INTF_CTL_DAC_FORMAT(x) (((x)&7)<<3) argument
69 #define CS42L51_MIC_CTL_MICBIAS_LVL(x) (((x)&3)<<2) argument
78 #define CS42L51_ADC_CTL_SOFTB (1<<3)
84 #define CS42L51_ADC_INPUT_AINB_MUX(x) (((x)&3)<<6) argument
85 #define CS42L51_ADC_INPUT_AINA_MUX(x) (((x)&3)<<4) argument
[all …]
/linux-6.12.1/Documentation/input/devices/
Dsentelic.rst20 3. Set sample rate to 80;
27 Bit 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
29 1 |Y|X|y|x|1|M|R|L| 2 |X|X|X|X|X|X|X|X| 3 |Y|Y|Y|Y|Y|Y|Y|Y| 4 | | |B|F|W|W|W|W|
33 Bit6 => X overflow
35 Bit4 => X sign bit
40 Byte 2: X Movement(9-bit 2's complement integers)
41 Byte 3: Y Movement(9-bit 2's complement integers)
59 Bit 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
61 1 |Y|X|y|x|1|M|R|L| 2 |X|X|X|X|X|X|X|X| 3 |Y|Y|Y|Y|Y|Y|Y|Y| 4 | | |B|F|r|l|u|d|
65 Bit6 => X overflow
[all …]
/linux-6.12.1/drivers/phy/rockchip/
Dphy-rockchip-inno-hdmi.c23 #define UPDATE(x, h, l) (((x) << (l)) & GENMASK((h), (l))) argument
36 #define RK3228_AUTO_TERM_RES_CAL_SPEED_14_8(x) UPDATE(x, 6, 0) argument
38 #define RK3228_AUTO_TERM_RES_CAL_SPEED_7_0(x) UPDATE(x, 7, 0) argument
44 #define RK3228_RXSENSE_CLK_CH_ENABLE BIT(3)
50 #define RK3228_TMDS_DRIVER_ENABLE GENMASK(3, 0)
53 #define RK3228_PRE_PLL_FB_DIV_8(x) UPDATE((x) >> 8, 7, 7) argument
55 #define RK3228_PCLK_VCO_DIV_5(x) UPDATE(x, 5, 5) argument
57 #define RK3228_PRE_PLL_PRE_DIV(x) UPDATE(x, 4, 0) argument
59 #define RK3228_PRE_PLL_FB_DIV_7_0(x) UPDATE(x, 7, 0) argument
63 #define RK3228_PRE_PLL_PCLK_DIV_B(x) UPDATE(x, 6, 5) argument
[all …]
/linux-6.12.1/arch/mips/include/asm/
Dpgtable-32.h78 # define __PGD_TABLE_ORDER (32 - 3 * PAGE_SHIFT + PGD_T_LOG2 + PTE_T_LOG2 + 1)
80 # define __PGD_TABLE_ORDER (32 - 3 * PAGE_SHIFT + PGD_T_LOG2 + PTE_T_LOG2)
156 #define pte_pfn(x) (((unsigned long)((x).pte_high >> PFN_PTE_SHIFT)) | (unsigned long)((x).pte_low… argument
172 #define pte_pfn(x) ((unsigned long)((x).pte_high >> 6)) argument
187 #define pte_pfn(x) ((unsigned long)((x).pte >> PFN_PTE_SHIFT)) argument
192 #define pte_page(x) pfn_to_page(pte_pfn(x)) argument
203 * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
204 * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
211 #define __swp_type(x) (((x).val >> 10) & 0x1f) argument
212 #define __swp_offset(x) ((x).val >> 15) argument
[all …]
/linux-6.12.1/drivers/gpu/drm/exynos/
Dregs-fimc.h28 /* Y 3rd frame start address for output DMA */
36 /* Cb 3rd frame start address for output DMA */
44 /* Cr 3rd frame start address for output DMA */
321 #define EXYNOS_CISRCFMT_SOURCEHSIZE(x) ((x) << 16) argument
322 #define EXYNOS_CISRCFMT_SOURCEVSIZE(x) ((x) << 0) argument
324 #define EXYNOS_CIWDOFST_WINHOROFST(x) ((x) << 16) argument
325 #define EXYNOS_CIWDOFST_WINVEROFST(x) ((x) << 0) argument
327 #define EXYNOS_CIWDOFST2_WINHOROFST2(x) ((x) << 16) argument
328 #define EXYNOS_CIWDOFST2_WINVEROFST2(x) ((x) << 0) argument
330 #define EXYNOS_CITRGFMT_TARGETHSIZE(x) (((x) & 0x1fff) << 16) argument
[all …]

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