input/devices/sentelic.rst

20 3. Set sample rate to 80;
27     Bit 7 6 5 4 3 2 1 0       7 6 5 4 3 2 1 0      7 6 5 4 3 2 1 0      7 6 5 4 3 2 1 0
29       1   |Y|X|y|x|1|M|R|L|  2  |X|X|X|X|X|X|X|X|  3 |Y|Y|Y|Y|Y|Y|Y|Y|  4 | | |B|F|W|W|W|W|
33 	    Bit6 => X overflow
35 	    Bit4 => X sign bit
40     Byte 2: X Movement(9-bit 2's complement integers)
41     Byte 3: Y Movement(9-bit 2's complement integers)
59     Bit 7 6 5 4 3 2 1 0       7 6 5 4 3 2 1 0      7 6 5 4 3 2 1 0      7 6 5 4 3 2 1 0
61       1   |Y|X|y|x|1|M|R|L|  2  |X|X|X|X|X|X|X|X|  3 |Y|Y|Y|Y|Y|Y|Y|Y|  4 | | |B|F|r|l|u|d|
65 	    Bit6 => X overflow
67 	    Bit4 => X sign bit
72     Byte 2: X Movement(9-bit 2's complement integers)
73     Byte 3: Y Movement(9-bit 2's complement integers)
97 1. Set bit 2 or 3 in register 0x40 to 1
103     Bit 7 6 5 4 3 2 1 0       7 6 5 4 3 2 1 0      7 6 5 4 3 2 1 0      7 6 5 4 3 2 1 0
105       1   |0|1|V|1|1|M|R|L|  2  |X|X|X|X|X|X|X|X|  3 |Y|Y|Y|Y|Y|Y|Y|Y|  4 |r|l|d|u|X|X|Y|Y|
117     Byte 2: X coordinate (xpos[9:2])
118     Byte 3: Y coordinate (ypos[9:2])
120 	    Bit3~Bit2 => X coordinate (ypos[1:0])
127     Bit 7 6 5 4 3 2 1 0       7 6 5 4 3 2 1 0      7 6 5 4 3 2 1 0      7 6 5 4 3 2 1 0
129       1   |1|0|0|1|1|M|R|L|  2  |C|C|C|C|C|C|C|C|  3 |M|M|M|M|M|M|M|M|  4 |0|0|0|0|0|0|0|0|
143     Byte 3: Message Type => 0x00 (Disabled)
155     Bit 7 6 5 4 3 2 1 0       7 6 5 4 3 2 1 0      7 6 5 4 3 2 1 0      7 6 5 4 3 2 1 0
157       1   |0|1|V|A|1|L|0|1|  2  |X|X|X|X|X|X|X|X|  3 |Y|Y|Y|Y|Y|Y|Y|Y|  4 |x|x|y|y|X|X|Y|Y|
172     Byte 2: X coordinate (xpos[9:2])
173     Byte 3: Y coordinate (ypos[9:2])
175 	    Bit3~Bit2 => X coordinate (ypos[1:0])
180     Bit 7 6 5 4 3 2 1 0       7 6 5 4 3 2 1 0      7 6 5 4 3 2 1 0      7 6 5 4 3 2 1 0
182       1   |0|1|V|A|1|R|1|0|  2  |X|X|X|X|X|X|X|X|  3 |Y|Y|Y|Y|Y|Y|Y|Y|  4 |x|x|y|y|X|X|Y|Y|
197     Byte 2: X coordinate (xpos[9:2])
198     Byte 3: Y coordinate (ypos[9:2])
200 	    Bit3~Bit2 => X coordinate (ypos[1:0])
205     Bit 7 6 5 4 3 2 1 0       7 6 5 4 3 2 1 0      7 6 5 4 3 2 1 0      7 6 5 4 3 2 1 0
207       1   |1|0|1|P|1|M|R|L|  2  |C|C|C|C|C|C|C|C|  3 |0|0|F|F|0|0|0|i|  4 |r|l|d|u|0|0|0|0|
223     Byte 3: Bit7~Bit6 => Don't care
247     Bit 7 6 5 4 3 2 1 0       7 6 5 4 3 2 1 0      7 6 5 4 3 2 1 0      7 6 5 4 3 2 1 0
249       1   |0|1|V|F|1|0|R|L|  2  |X|X|X|X|X|X|X|X|  3 |Y|Y|Y|Y|Y|Y|Y|Y|  4 |r|l|u|d|X|X|Y|Y|
264     Byte 2: X coordinate (xpos[9:2])
265     Byte 3: Y coordinate (ypos[9:2])
267 	    Bit3~Bit2 => X coordinate (ypos[1:0])
274     Bit 7 6 5 4 3 2 1 0       7 6 5 4 3 2 1 0      7 6 5 4 3 2 1 0      7 6 5 4 3 2 1 0
276       1   |0|1|V|F|1|1|R|L|  2  |X|X|X|X|X|X|X|X|  3 |Y|Y|Y|Y|Y|Y|Y|Y|  4 |r|l|u|d|X|X|Y|Y|
291     Byte 2: X coordinate (xpos[9:2])
292     Byte 3: Y coordinate (ypos[9:2])
294 	    Bit3~Bit2 => X coordinate (ypos[1:0])
302     Bit 7 6 5 4 3 2 1 0       7 6 5 4 3 2 1 0      7 6 5 4 3 2 1 0      7 6 5 4 3 2 1 0
304       1   |1|0|1|P|1|M|R|L|  2  |C|C|C|C|C|C|C|C|  3 |0|0|F|F|0|0|0|i|  4 |r|l|u|d|0|0|0|0|
320     Byte 3: Bit7~Bit6 => Don't care
344     Bit 7 6 5 4 3 2 1 0       7 6 5 4 3 2 1 0      7 6 5 4 3 2 1 0      7 6 5 4 3 2 1 0
346       1   |0|1|0|P|1|M|R|L|  2  |X|X|X|X|X|X|X|X|  3 |Y|Y|Y|Y|Y|Y|Y|Y|  4 |r|l|B|F|X|X|Y|Y|
362     Byte 2: X coordinate (xpos[9:2])
363     Byte 3: Y coordinate (ypos[9:2])
365 	    Bit3~Bit2 => X coordinate (ypos[1:0])
372     Bit 7 6 5 4 3 2 1 0       7 6 5 4 3 2 1 0      7 6 5 4 3 2 1 0      7 6 5 4 3 2 1 0
374       1   |0|1|1|P|1|F|R|L|  2  |X|X|X|X|X|X|X|X|  3 |Y|Y|Y|Y|Y|Y|Y|Y|  4 |r|l|B|F|X|X|Y|Y|
392     Byte 2: X coordinate (xpos[9:2])
393     Byte 3: Y coordinate (ypos[9:2])
395 	    Bit3~Bit2 => X coordinate (ypos[1:0])
402 MFMC#0 report packets with zero X and Y to represent 1st finger is up or
403 four consecutive MFMC#1 report packets with zero X and Y to represent that
406 with zero X and Y.
410     Bit 7 6 5 4 3 2 1 0       7 6 5 4 3 2 1 0      7 6 5 4 3 2 1 0      7 6 5 4 3 2 1 0
412       1   |1|0|0|P|1|M|R|L|  2  |C|C|C|C|C|C|C|C|  3 |0|0|F|F|0|0|0|i|  4 |r|l|u|d|0|0|0|0|
429     Byte 3: The first parameter for the received message:
450     Bit 7 6 5 4 3 2 1 0       7 6 5 4 3 2 1 0      7 6 5 4 3 2 1 0      7 6 5 4 3 2 1 0
452       1   |Y|X|0|0|1|M|R|L|  2  |0|1|0|1|1|0|1|E|  3 | | | | | | | | |  4 | | | | | | | | |
461 	    Bit6 => 0, X overflow
463 	    Bit4 => 0, X sign bit
471     Byte 3: Don't care
472     Byte 4: Don't care (MOUSE ID 3, 4)
506 3. For FSP version >= STL3888 Cx:
533 	3. send 0x88 PS/2 command to FSP;
566 	  complement of the register value at the 3rd byte of status request
578 	goto step 3
584 	3. if the register address being to write is not required to be
621 	  complement of the register value at the 3rd byte of status request
648 	3. send 0x88 PS/2 command to FSP;
667 	3. send 0x88 PS/2 command to FSP;
712 	0x2e	3 finger straight up
713 	0x2a	3 finger straight down
714 	0x28	3 finger straight right
715 	0x2c	3 finger straight left
822 	In addition, when bit 1, bit 2 and bit 3 are set at the same time,
823 	bit 3 will override bit 1 and 2.)
833 	bit 2 and 3.  That is, if any of those bit is 1, host will receive
846 	(Note that if this bit is cleared, bit 3/5 will be ineffective)