Lines Matching +full:3 +full:x
33 #define PACKET_TYPE3 3
35 #define CP_PACKET_GET_TYPE(h) (((h) >> 30) & 3)
54 /* Packet 3 types */
57 #define PACKET3_BASE_INDEX(x) ((x) << 0) argument
58 #define CE_PARTITION_BASE 3
89 #define WRITE_DATA_DST_SEL(x) ((x) << 8) argument
93 * 3 - gds
99 #define WRITE_DATA_CACHE_POLICY(x) ((x) << 25) argument
103 #define WRITE_DATA_ENGINE_SEL(x) ((x) << 30) argument
117 #define WAIT_REG_MEM_FUNCTION(x) ((x) << 0) argument
121 * 3 - ==
126 #define WAIT_REG_MEM_MEM_SPACE(x) ((x) << 4) argument
130 #define WAIT_REG_MEM_OPERATION(x) ((x) << 6) argument
134 #define WAIT_REG_MEM_ENGINE(x) ((x) << 8) argument
140 #define INDIRECT_BUFFER_CACHE_POLICY(x) ((x) << 28) argument
145 #define INDIRECT_BUFFER_PRE_ENB(x) ((x) << 21) argument
146 #define INDIRECT_BUFFER_PRE_RESUME(x) ((x) << 30) argument
155 #define EVENT_TYPE(x) ((x) << 0) argument
156 #define EVENT_INDEX(x) ((x) << 8) argument
160 * 3 - SAMPLE_STREAMOUTSTAT*
166 #define PACKET3_RELEASE_MEM_EVENT_TYPE(x) ((x) << 0) argument
167 #define PACKET3_RELEASE_MEM_EVENT_INDEX(x) ((x) << 8) argument
178 #define PACKET3_RELEASE_MEM_CACHE_POLICY(x) ((x) << 25) argument
182 * 3 - cache_policy__me_release_mem__bypass
186 #define PACKET3_RELEASE_MEM_DATA_SEL(x) ((x) << 29) argument
190 * 3 - send 64bit GPU counter value
193 #define PACKET3_RELEASE_MEM_INT_SEL(x) ((x) << 24) argument
198 #define PACKET3_RELEASE_MEM_DST_SEL(x) ((x) << 16) argument
207 # define PACKET3_PREAMBLE_END_CLEAR_STATE (3 << 28)
211 * 3. SRC_ADDR_LO or DATA [31:0]
218 # define PACKET3_DMA_DATA_ENGINE(x) ((x) << 0) argument
222 # define PACKET3_DMA_DATA_SRC_CACHE_POLICY(x) ((x) << 13) argument
226 # define PACKET3_DMA_DATA_DST_SEL(x) ((x) << 20) argument
229 * 3 - DST_ADDR using L2
231 # define PACKET3_DMA_DATA_DST_CACHE_POLICY(x) ((x) << 25) argument
235 # define PACKET3_DMA_DATA_SRC_SEL(x) ((x) << 29) argument
239 * 3 - SRC_ADDR using L2
263 * 3. COHER_SIZE_HI [7:0]
269 #define PACKET3_ACQUIRE_MEM_GCR_CNTL_GLI_INV(x) ((x) << 0) argument
274 * 3:FIRST_LAST
276 #define PACKET3_ACQUIRE_MEM_GCR_CNTL_GL1_RANGE(x) ((x) << 2) argument
281 * 3:FIRST_LAST
283 #define PACKET3_ACQUIRE_MEM_GCR_CNTL_GLM_WB(x) ((x) << 4) argument
284 #define PACKET3_ACQUIRE_MEM_GCR_CNTL_GLM_INV(x) ((x) << 5) argument
285 #define PACKET3_ACQUIRE_MEM_GCR_CNTL_GLK_WB(x) ((x) << 6) argument
286 #define PACKET3_ACQUIRE_MEM_GCR_CNTL_GLK_INV(x) ((x) << 7) argument
287 #define PACKET3_ACQUIRE_MEM_GCR_CNTL_GLV_INV(x) ((x) << 8) argument
288 #define PACKET3_ACQUIRE_MEM_GCR_CNTL_GL1_INV(x) ((x) << 9) argument
289 #define PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_US(x) ((x) << 10) argument
290 #define PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_RANGE(x) ((x) << 11) argument
295 * 3:FIRST_LAST
297 #define PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_DISCARD(x) ((x) << 13) argument
298 #define PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_INV(x) ((x) << 14) argument
299 #define PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_WB(x) ((x) << 15) argument
300 #define PACKET3_ACQUIRE_MEM_GCR_CNTL_SEQ(x) ((x) << 16) argument
358 # define FRAME_CMD(x) ((x) << 28) argument
360 * x=0: tmz_begin
361 * x=1: tmz_end
369 # define PACKET3_INVALIDATE_TLBS_DST_SEL(x) ((x) << 0) argument
370 # define PACKET3_INVALIDATE_TLBS_ALL_HUB(x) ((x) << 4) argument
371 # define PACKET3_INVALIDATE_TLBS_PASID(x) ((x) << 5) argument
382 * 3. QUEUE_MASK_LO [31:0]
389 # define PACKET3_SET_RESOURCES_VMID_MASK(x) ((x) << 0) argument
390 # define PACKET3_SET_RESOURCES_UNMAP_LATENTY(x) ((x) << 16) argument
391 # define PACKET3_SET_RESOURCES_QUEUE_TYPE(x) ((x) << 29) argument
396 * 3. CONTROL2
403 # define PACKET3_MAP_QUEUES_QUEUE_SEL(x) ((x) << 4) argument
404 # define PACKET3_MAP_QUEUES_VMID(x) ((x) << 8) argument
405 # define PACKET3_MAP_QUEUES_QUEUE(x) ((x) << 13) argument
406 # define PACKET3_MAP_QUEUES_PIPE(x) ((x) << 16) argument
407 # define PACKET3_MAP_QUEUES_ME(x) ((x) << 18) argument
408 # define PACKET3_MAP_QUEUES_QUEUE_TYPE(x) ((x) << 21) argument
409 # define PACKET3_MAP_QUEUES_ALLOC_FORMAT(x) ((x) << 24) argument
410 # define PACKET3_MAP_QUEUES_ENGINE_SEL(x) ((x) << 26) argument
411 # define PACKET3_MAP_QUEUES_NUM_QUEUES(x) ((x) << 29) argument
413 # define PACKET3_MAP_QUEUES_CHECK_DISABLE(x) ((x) << 1) argument
414 # define PACKET3_MAP_QUEUES_DOORBELL_OFFSET(x) ((x) << 2) argument
418 * 3. CONTROL2
424 # define PACKET3_UNMAP_QUEUES_ACTION(x) ((x) << 0) argument
428 * 3 - PREEMPT_QUEUES_NO_UNMAP
430 # define PACKET3_UNMAP_QUEUES_QUEUE_SEL(x) ((x) << 4) argument
431 # define PACKET3_UNMAP_QUEUES_ENGINE_SEL(x) ((x) << 26) argument
432 # define PACKET3_UNMAP_QUEUES_NUM_QUEUES(x) ((x) << 29) argument
434 # define PACKET3_UNMAP_QUEUES_PASID(x) ((x) << 0) argument
436 # define PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET0(x) ((x) << 2) argument
438 # define PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET1(x) ((x) << 2) argument
440 # define PACKET3_UNMAP_QUEUES_RB_WPTR(x) ((x) << 0) argument
442 # define PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET2(x) ((x) << 2) argument
444 # define PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET3(x) ((x) << 2) argument
448 * 3. CONTROL2
455 # define PACKET3_QUERY_STATUS_CONTEXT_ID(x) ((x) << 0) argument
456 # define PACKET3_QUERY_STATUS_INTERRUPT_SEL(x) ((x) << 28) argument
457 # define PACKET3_QUERY_STATUS_COMMAND(x) ((x) << 30) argument
459 # define PACKET3_QUERY_STATUS_PASID(x) ((x) << 0) argument
461 # define PACKET3_QUERY_STATUS_DOORBELL_OFFSET(x) ((x) << 2) argument
462 # define PACKET3_QUERY_STATUS_ENG_SEL(x) ((x) << 25) argument
467 # define PACKET3_SET_Q_PREEMPTION_MODE_IB_VMID(x) ((x) << 0) argument