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/linux-6.12.1/arch/parisc/include/asm/
Dassembly.h26 /* Frame alignment for 32- and 64-bit */
62 #define LDREGM ldd,mb
136 zdep \r, 31-(\sa), 32-(\sa), \t
144 /* Shift Right for 32-bit. Clobbers upper 32-bit on PA2.0. */
146 extru \r, 31-(\sa), 32-(\sa), \t
154 /* Extract unsigned for 32- and 64-bit
155 * The extru instruction leaves the most significant 32 bits of the
159 extrd,u \r, 32+(\p), \len, \t
165 /* The depi instruction leaves the most significant 32 bits of the
169 depdi \i, 32+(\p), \len, \t
[all …]
/linux-6.12.1/tools/testing/selftests/tc-testing/tc-tests/qdiscs/
Dfq_codel.json17 …]+ limit 10240p flows 1024 quantum.*target 5ms interval 100ms memory_limit 32Mb ecn drop_batch 64",
38 …9]+ limit 1000p flows 1024 quantum.*target 5ms interval 100ms memory_limit 32Mb ecn drop_batch 64",
80 …]+ limit 10240p flows 1024 quantum.*target 2ms interval 100ms memory_limit 32Mb ecn drop_batch 64",
101 …-9]+ limit 10240p flows 1024 quantum.*target 5ms interval 5ms memory_limit 32Mb ecn drop_batch 64",
122 …imit 10240p flows 1024 quantum 9000 target 5ms interval 100ms memory_limit 32Mb ecn drop_batch 64",
143 …[0-9]+ limit 10240p flows 1024 quantum.*target 5ms interval 100ms memory_limit 32Mb drop_batch 64",
164 …ws 1024 quantum.*target 5ms ce_threshold 1.02s interval 100ms memory_limit 32Mb ecn drop_batch 64",
185 …+ limit 10240p flows 1024 quantum.*target 5ms interval 100ms memory_limit 32Mb ecn drop_batch 100",
206 …9]+ limit 1000p flows 256 quantum.*target 5ms interval 100ms memory_limit 32Mb ecn drop_batch 100",
228 … [0-9]+ limit 1000p flows 256 quantum.*target 5ms interval 100ms memory_limit 32Mb drop_batch 100",
[all …]
/linux-6.12.1/Documentation/admin-guide/cgroup-v1/
Dhugetlb.rst34 For a system supporting three hugepage sizes (64k, 32M and 1G), the control
55 hugetlb.32MB.limit_in_bytes
56 hugetlb.32MB.max_usage_in_bytes
57 hugetlb.32MB.numa_stat
58 hugetlb.32MB.usage_in_bytes
59 hugetlb.32MB.failcnt
60 hugetlb.32MB.rsvd.limit_in_bytes
61 hugetlb.32MB.rsvd.max_usage_in_bytes
62 hugetlb.32MB.rsvd.usage_in_bytes
63 hugetlb.32MB.rsvd.failcnt
/linux-6.12.1/arch/x86/kernel/
Dearly-quirks.c243 #define MB(x) (KB (KB (x))) macro
253 return MB(1); in i830_tseg_size()
268 case I845_TSEG_SIZE_1M: return MB(1); in i845_tseg_size()
282 return MB(1); in i85x_tseg_size()
287 return read_pci_config_byte(0, 0, 0, I830_DRB3) * MB(32); in i830_mem_size()
292 return read_pci_config_byte(0, 0, 1, I85X_DRB3) * MB(32); in i85x_mem_size()
349 bsm |= (u64)read_pci_config(num, slot, func, INTEL_GEN11_BSM_DW1) << 32; in gen11_stolen_base()
364 case I830_GMCH_GMS_STOLEN_1024: return MB(1); in i830_stolen_size()
365 case I830_GMCH_GMS_STOLEN_8192: return MB(8); in i830_stolen_size()
384 case I855_GMCH_GMS_STOLEN_1M: return MB(1); in gen3_stolen_size()
[all …]
/linux-6.12.1/drivers/accel/habanalabs/include/gaudi2/
Dgaudi2.h16 #define CFG_BAR_SIZE 0x10000000ull /* 256MB */
21 #define CFG_SIZE 0x8000000ull /* 96MB CFG + 32MB DBG*/
22 #define CFG_REGION_SIZE 0xC000000ull /* 192MB */
24 #define STM_FLASH_BASE_ADDR 0x1000007FF4000000ull /* Not 256MB aligned */
25 #define STM_FLASH_ALIGNED_OFF 0x4000000ull /* 256 MB alignment */
26 #define STM_FLASH_SIZE 0x2000000ull /* 32MB */
29 #define SPI_FLASH_SIZE 0x1000000ull /* 16MB */
35 #define PCIE_FW_SRAM_SIZE 0x8000 /* 32KB */
38 #define BAR0_RSRVD_SIZE 0x1000000ull /* 16MB */
41 #define SRAM_SIZE 0x3000000ull /* 48MB */
/linux-6.12.1/drivers/accel/habanalabs/include/gaudi/
Dgaudi.h15 #define SRAM_BAR_SIZE 0x4000000ull /* 64MB */
16 #define CFG_BAR_SIZE 0x8000000ull /* 128MB */
19 #define CFG_SIZE 0x4000000 /* 32MB CFG + 32MB DBG*/
22 #define SRAM_SIZE 0x1400000 /* 20MB */
30 #define PCIE_FW_SRAM_SIZE 0x8000 /* 32KB */
37 #define GAUDI_MSI_ENTRIES 32
/linux-6.12.1/Documentation/fb/
Dmatroxfb.rst53 32 0x112 0x183 0x115 0x18B
68 32 0x118 0x193 0x11B 0x19B
87 example 1600x1200x32bpp can be specified by `video=matroxfb:vesa:0x11C,depth:32`.
94 architectures there are some glitches for 24bpp videomodes. 8, 16 and 32bpp
128 memory usable for on-screen display (i.e. max. 8 MB).
143 transaction terminate with success or retry in 32 PCLK).
165 - 0 -> 2x128Kx32 chips, 2MB onboard, probably sgram
166 - 1 -> 2x128Kx32 chips, 4MB onboard, probably sgram
167 - 2 -> 2x256Kx32 chips, 4MB onboard, probably sgram
168 - 3 -> 2x256Kx32 chips, 8MB onboard, probably sgram
[all …]
/linux-6.12.1/drivers/eisa/
Deisa.ids14 ACC1200 "ACCTON EtherCombo-32 Ethernet Adapter"
15 ACC120A "ACCTON EtherCombo-32 Ethernet Adapter"
50 ADI0001 "Lightning Networks 32-Bit EISA Ethernet LAN Adapter"
55 AIM0002 "AUVA OPTi/EISA 32-Bit 486 All-in-One System Board"
134 BUS4201 "BusTek/BusLogic Bt74xB 32-Bit Bus Master EISA-to-SCSI Host Adapter"
135 BUS4202 "BusTek/BusLogic Bt74xC 32-Bit Bus Master EISA-to-SCSI Host Adapter"
136 BUS6001 "BusTek/BusLogic Bt760 32-Bit Bus Master EISA-to-Ethernet Controller"
137 BUS6301 "BusTek/BusLogic Bt763E EISA 32-Bit 82596-based Ethernet Controller"
155 CNT2000 "900E/950E EISA Bus 32-bit Ethernet LAN Adapter"
158 COG9002 "Cogent eMASTER+ EISA XL 32-Bit Burst-mode Ethernet Adapter"
[all …]
/linux-6.12.1/arch/mips/include/asm/sgi/
Dgio.h20 * There is 10MB of GIO address space for GIO64 slot devices
23 * 0 GFX 0x1f000000 - 0x1f3fffff 4MB
24 * 1 EXP0 0x1f400000 - 0x1f5fffff 2MB
25 * 2 EXP1 0x1f600000 - 0x1f9fffff 4MB
29 * - MISC 0x1fb00000 - 0x1fbfffff 1MB
32 * - RESERVED 0x18000000 - 0x1effffff 112MB
37 * read with an "ID" value. IDs are either 8 or 32 bits long. IDs less
41 * 32-bit IDs are divided into
44 * 1=GIO Product ID is 32 bits wide.
71 * [*] Device provide 32-bit ID.
/linux-6.12.1/arch/x86/kernel/cpu/
Dcacheinfo.c53 #define MB(x) ((x) * 1024) macro
60 { 0x06, LVL_1_INST, 8 }, /* 4-way set assoc, 32 byte line size */
61 { 0x08, LVL_1_INST, 16 }, /* 4-way set assoc, 32 byte line size */
62 { 0x09, LVL_1_INST, 32 }, /* 4-way set assoc, 64 byte line size */
63 { 0x0a, LVL_1_DATA, 8 }, /* 2 way set assoc, 32 byte line size */
64 { 0x0c, LVL_1_DATA, 16 }, /* 4-way set assoc, 32 byte line size */
69 { 0x23, LVL_3, MB(1) }, /* 8-way set assoc, sectored cache, 64 byte line size */
70 { 0x25, LVL_3, MB(2) }, /* 8-way set assoc, sectored cache, 64 byte line size */
71 { 0x29, LVL_3, MB(4) }, /* 8-way set assoc, sectored cache, 64 byte line size */
72 { 0x2c, LVL_1_DATA, 32 }, /* 8-way set assoc, 64 byte line size */
[all …]
/linux-6.12.1/arch/arm64/include/asm/
Datomic_ll_sc.h42 #define ATOMIC_OP_RETURN(name, mb, acq, rel, cl, op, asm_op, constraint)\ argument
55 " " #mb \
63 #define ATOMIC_FETCH_OP(name, mb, acq, rel, cl, op, asm_op, constraint) \ argument
76 " " #mb \
138 #define ATOMIC64_OP_RETURN(name, mb, acq, rel, cl, op, asm_op, constraint)\ argument
151 " " #mb \
159 #define ATOMIC64_FETCH_OP(name, mb, acq, rel, cl, op, asm_op, constraint)\ argument
172 " " #mb \
239 #define __CMPXCHG_CASE(w, sfx, name, sz, mb, acq, rel, cl, constraint) \ argument
253 if (sz < 32) \
[all …]
Datomic_lse.h36 #define ATOMIC_FETCH_OP(name, mb, op, asm_op, cl...) \ argument
44 " " #asm_op #mb " %w[i], %w[old], %[v]" \
106 #define ATOMIC_FETCH_OP_AND(name, mb, cl...) \ argument
143 #define ATOMIC64_FETCH_OP(name, mb, op, asm_op, cl...) \ argument
151 " " #asm_op #mb " %[i], %[old], %[v]" \
213 #define ATOMIC64_FETCH_OP_AND(name, mb, cl...) \ argument
248 #define __CMPXCHG_CASE(w, sfx, name, sz, mb, cl...) \ argument
256 " cas" #mb #sfx " %" #w "[old], %" #w "[new], %[v]\n" \
267 __CMPXCHG_CASE(w, , , 32, )
271 __CMPXCHG_CASE(w, , acq_, 32, a, "memory")
[all …]
/linux-6.12.1/drivers/accel/habanalabs/include/goya/
Dgoya.h15 #define CFG_BAR_SIZE 0x10000000ull /* 256MB */
19 #define CFG_SIZE 0x4000000 /* 32MB CFG + 32MB DBG*/
22 #define SRAM_SIZE 0x32A0000 /* 50.625MB */
/linux-6.12.1/arch/alpha/kernel/
Dcore_cia.c34 * NOTE: Herein lie back-to-back mb instructions. They are magic.
84 * The register selects a DWORD (32 bit) register offset. Hence it
118 mb(); in conf_read()
125 mb(); in conf_read()
129 mb(); in conf_read()
133 mb(); in conf_read()
137 mb(); in conf_read()
138 mb(); /* magic */ in conf_read()
142 mb(); in conf_read()
145 mb(); in conf_read()
[all …]
Dio.c20 mb(); in ioread8()
22 mb(); in ioread8()
29 mb(); in ioread16()
31 mb(); in ioread16()
38 mb(); in ioread32()
40 mb(); in ioread32()
47 mb(); in ioread64()
49 mb(); in ioread64()
55 mb(); in iowrite8()
61 mb(); in iowrite16()
[all …]
/linux-6.12.1/arch/powerpc/lib/
Dtest-code-patching.c62 /* Maximum positive relative branch, + 20MB - 4B */ in test_branch_iform()
68 /* Largest negative relative branch, - 32 MB */ in test_branch_iform()
87 /* Maximum relative negative offset, - 32 MB */ in test_branch_iform()
92 /* Out of range relative negative offset, - 32 MB + 4*/ in test_branch_iform()
96 /* Out of range relative positive offset, + 32 MB */ in test_branch_iform()
151 /* Maximum positive relative conditional branch, + 32 KB - 4B */ in test_branch_bform()
157 /* Largest negative relative conditional branch, - 32 KB */ in test_branch_bform()
179 /* Maximum relative negative offset, - 32 KB */ in test_branch_bform()
184 /* Out of range relative negative offset, - 32 KB + 4*/ in test_branch_bform()
188 /* Out of range relative positive offset, + 32 KB */ in test_branch_bform()
[all …]
/linux-6.12.1/Documentation/arch/powerpc/
Dpci_iov_resource_on_powernv.rst64 the 32-bit space and one much higher) which, via a combination of the
87 32-bit PCIe accesses. We configure that window at boot from FW and
98 the segment granularity is 2GB/256 = 8MB.
112 * Must be at least 256MB in size.
141 update the M32 PE# for the devices that use both 32-bit and 64-bit
142 spaces or assign the remaining PE# to 32-bit only devices.
180 1MB VF BAR0, the address in that VF BAR sets the base of an 8MB region.
181 This region is divided into eight contiguous 1MB regions, each of which
183 describes an 8MB region, the alignment requirement is for a single VF,
184 i.e., 1MB in this example.
[all …]
/linux-6.12.1/arch/powerpc/kernel/
Dcrash_dump.c42 * instruction's address + (32 MB - 4) bytes. For the trampoline we in create_trampoline()
43 * need to branch to current address + 32 MB. So we insert a nop at in create_trampoline()
45 * does a branch to (32 MB - 4). The net effect is that when we in create_trampoline()
46 * branch to "addr" we jump to ("addr" + 32 MB). Although it requires in create_trampoline()
/linux-6.12.1/include/linux/bcma/
Dbcma_regs.h76 #define BCMA_SOC_PCI_MEM 0x08000000U /* Host Mode sb2pcitranslation0 (64 MB) */
78 #define BCMA_SOC_PCI_CFG 0x0c000000U /* Host Mode sb2pcitranslation1 (64 MB) */
80 #define BCMA_SOC_SDRAM_R2 0x80000000U /* Region 2 for sdram (512 MB) */
87 * (2 ZettaBytes), low 32 bits
90 * (2 ZettaBytes), high 32 bits
93 #define BCMA_SOC_PCI1_MEM 0x40000000U /* Host Mode sb2pcitranslation0 (64 MB) */
94 #define BCMA_SOC_PCI1_CFG 0x44000000U /* Host Mode sb2pcitranslation1 (64 MB) */
96 * (2 ZettaBytes), high 32 bits
/linux-6.12.1/sound/isa/gus/
Dgus_io.c17 mb(); in snd_gf1_delay()
36 mb(); in __snd_gf1_ctrl_stop()
38 mb(); in __snd_gf1_ctrl_stop()
40 mb(); in __snd_gf1_ctrl_stop()
42 mb(); in __snd_gf1_ctrl_stop()
50 mb(); in __snd_gf1_write8()
52 mb(); in __snd_gf1_write8()
59 mb(); in __snd_gf1_look8()
67 mb(); in __snd_gf1_write16()
69 mb(); in __snd_gf1_write16()
[all …]
/linux-6.12.1/Documentation/arch/x86/x86_64/
Dmm.rst20 from TB to GB and then MB/KB.
47 ffffc90000000000 | -55 TB | ffffe8ffffffffff | 32 TB | vmalloc/ioremap space (vmalloc_base)
65 …ffffffff80000000 | -2 GB | ffffffff9fffffff | 512 MB | kernel text mapping, mapped to physic…
66 ffffffff80000000 |-2048 MB | | |
67 ffffffffa0000000 |-1536 MB | fffffffffeffffff | 1520 MB | module mapping space
68 ffffffffff000000 | -16 MB | | |
69 …FIXADDR_START | ~-11 MB | ffffffffff5fffff | ~0.5 MB | kernel-internal fixmap range, variable s…
70 ffffffffff600000 | -10 MB | ffffffffff600fff | 4 kB | legacy vsyscall ABI
71 ffffffffffe00000 | -2 MB | ffffffffffffffff | 2 MB | ... unused hole
104 …ff11000000000000 | -59.75 PB | ff90ffffffffffff | 32 PB | direct mapping of all physical memory…
[all …]
/linux-6.12.1/arch/sparc/include/asm/
Dtsb.h49 #define TSB_TAG_LOCK_HIGH (1 << (TSB_TAG_LOCK_BIT - 32))
52 #define TSB_TAG_INVALID_HIGH (1 << (TSB_TAG_INVALID_BIT - 32))
151 * bit 23, for 8MB per PMD) we must propagate bit 22 for a
152 * 4MB huge page. For huge PUDs (which fall on bit 33, for
153 * 8GB per PUD), we have to accommodate 256MB and 2GB huge
154 * pages. So for those we propagate bits 32 to 28.
171 sllx REG2, 32, REG2; \
182 sllx REG2, 32, REG2; \
204 * We have to propagate bits [32:22] from the virtual address
217 sllx REG2, 32, REG2; \
[all …]
/linux-6.12.1/tools/perf/pmu-events/arch/arm64/arm/cmn/sys/
Dmetric.json42 "MetricExpr": "rnid_rxdat_flits * 32 / 1e6 / duration_time",
43 "ScaleUnit": "1MB/s",
51 "MetricExpr": "rnid_txdat_flits * 32 / 1e6 / duration_time",
52 "ScaleUnit": "1MB/s",
69 "MetricExpr": "sbsx_txdat_flitv * 32 / 1e6 / duration_time",
70 "ScaleUnit": "1MB/s",
/linux-6.12.1/drivers/media/pci/intel/ipu6/
Dipu6.h71 #define IPU6_DEVICE_GDA_VIRT_FACTOR 32
95 #define IPU6_MMU_ADDR_BITS 32
99 #define IPU6_MMU_MAX_TLB_L1_STREAMS 32
100 #define IPU6_MMU_MAX_TLB_L2_STREAMS 32
152 * L2 -> 16 streams and 32 blocks. 2 blocks per streams
153 * One L2 block maps to 1024 L1 entries, hence points to 4MB address range
154 * 2 blocks per L2 stream means, 1 stream points to 8MB range
156 * As we need to clear the caches and 8MB being the biggest cache size, we need
157 * to have trash buffer which points to 8MB address range. As these trash
159 * amount of physical memory. So we reserve 8MB IOVA address range but only
[all …]
/linux-6.12.1/arch/arc/plat-axs10x/
Daxs10x.c44 * | snps,dw-apb-intc (MB)| in axs10x_enable_gpio_intc_wire()
55 * DT hardware topology - connect MB intc directly to cpu intc in axs10x_enable_gpio_intc_wire()
94 char mb[32]; in axs10x_early_init() local
104 scnprintf(mb, 32, "MainBoard v%d", mb_rev); in axs10x_early_init()
105 axs10x_print_board_ver(CREG_MB_VER, mb); in axs10x_early_init()
121 * Each AXI master has a 4GB memory map specified as 16 apertures of 256MB, each
122 * of which maps to a corresponding 256MB aperture in Target slave memory map.
127 * Access from cpu to MB controllers such as GMAC is setup using AXI Tunnel:
131 * MB AXI Tunnel Master, which also has a mem map setup
133 * In the reverse direction, MB AXI Masters (e.g. GMAC) mem map is setup
[all …]

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