Lines Matching +full:32 +full:mb

71 #define IPU6_DEVICE_GDA_VIRT_FACTOR	32
95 #define IPU6_MMU_ADDR_BITS		32
99 #define IPU6_MMU_MAX_TLB_L1_STREAMS	32
100 #define IPU6_MMU_MAX_TLB_L2_STREAMS	32
152  * L2 -> 16 streams and 32 blocks. 2 blocks per streams
153  * One L2 block maps to 1024 L1 entries, hence points to 4MB address range
154  * 2 blocks per L2 stream means, 1 stream points to 8MB range
156  * As we need to clear the caches and 8MB being the biggest cache size, we need
157  * to have trash buffer which points to 8MB address range. As these trash
159  * amount of physical memory. So we reserve 8MB IOVA address range but only
160  * one page is reserved from physical memory. Each of this 8MB IOVA address