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/linux-6.12.1/Documentation/translations/zh_CN/core-api/
Dpacking.rst1 .. SPDX-License-Identifier: GPL-2.0+
3 .. include:: ../disclaimer-zh_CN.rst
5 :Original: Documentation/core-api/packing.rst
22 --------
42 --------
46 - 将一个CPU可使用的数字打包到内存缓冲区中（具有硬件约束/特殊性）。
47 - 将内存缓冲区（具有硬件约束/特殊性）解压缩为一个CPU可使用的数字。
61 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
75 56 57 58 59 60 61 62 63 48 49 50 51 52 53 54 55 40 41 42 43 44 45 46 47 32 33 34 35 36 37 38 39
87 39 38 37 36 35 34 33 32 47 46 45 44 43 42 41 40 55 54 53 52 51 50 49 48 63 62 61 60 59 58 57 56
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/linux-6.12.1/Documentation/core-api/
Dpacking.rst6 -----------------
10 One can memory-map a pointer to a carefully crafted struct over the hardware
23 were performed byte-by-byte. Also the code can easily get cluttered, and the
24 high-level idea might get lost among the many bit shifts required.
25 Many drivers take the bit-shifting approach and then attempt to reduce the
30 ------------
34 - Packing a CPU-usable number into a memory buffer (with hardware
36 - Unpacking a memory buffer (which has hardware constraints/quirks)
37 into a CPU-usable number.
55 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
[all …]
/linux-6.12.1/drivers/infiniband/hw/irdma/
Ddefs.h1 /* SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB */
2 /* Copyright (c) 2015 - 2021 Intel Corporation */
123 ((IRDMA_QP_SW_MAX_WQ_QUANTA - IRDMA_SQ_RSVD) / (max_quanta_per_wr))
141 #define IRDMA_QP_WQE_MIN_SIZE 32
198 IRDMA_OP_MC_DESTROY = 32,
360 (((u64)(val) << (dev)->hw_shifts[field ## _S]) & (dev)->hw_masks[field ## _M])
362 ((u64)((val) & (dev)->hw_masks[field ## _M]) >> (dev)->hw_shifts[field ## _S])
364 (((val) << (dev)->hw_shifts[field ## _S]) & (dev)->hw_masks[field ## _M])
366 ((u64)((val) & (dev)->hw_masks[field ## _M]) >> (dev)->hw_shifts[field ## _S])
375 #define IRDMA_CQPSQ_QHASH_VLANID GENMASK_ULL(43, 32)
[all …]
Duda_d.h1 /* SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB */
2 /* Copyright (c) 2016 - 2021 Intel Corporation */
24 #define IRDMA_UDA_QPSQ_LOCAL_FENCE BIT_ULL(61)
27 #define IRDMA_UDA_QPSQ_EXTHDRLEN GENMASK_ULL(40, 32)
70 #define IRDMA_UDAQPC_SQHDRRINGBUFSIZE GENMASK_ULL(33, 32)
78 #define IRDMA_UDAQPC_IPID GENMASK_ULL(47, 32)
86 #define IRDMA_UDA_CQPSQ_MAV_TC GENMASK_ULL(39, 32)
87 #define IRDMA_UDA_CQPSQ_MAV_HOPLIMIT GENMASK_ULL(39, 32)
89 #define IRDMA_UDA_CQPSQ_MAV_ADDR0 GENMASK_ULL(63, 32)
91 #define IRDMA_UDA_CQPSQ_MAV_ADDR2 GENMASK_ULL(63, 32)
[all …]
/linux-6.12.1/drivers/staging/media/ipu3/
Dipu3-tables.c1 // SPDX-License-Identifier: GPL-2.0
4 #include "ipu3-tables.h"
10 /* Scale factor 32 / (32 + 0) = 1 */
22 /* Scale factor 32 / (32 + 1) = 0.969697 */
25 { 0, 0, 122, 7, 7, -1, 0 },
26 { 0, -3, 122, 7, 10, -1, 0 },
27 { 0, -5, 121, 7, 14, -2, 0 },
28 { 0, -7, 120, 7, 18, -3, 0 },
29 { 0, -9, 118, 7, 23, -4, 0 },
30 { 0, -11, 116, 7, 27, -4, 0 },
[all …]
/linux-6.12.1/arch/mips/include/asm/octeon/
Dcvmx-rst-defs.h7 * Copyright (c) 2003-2014 Cavium Inc.
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
150 uint64_t reserved_32_63:32;
156 uint64_t reserved_32_63:32;
165 uint64_t reserved_32_63:32;
166 uint64_t eco_rw:32;
168 uint64_t eco_rw:32;
169 uint64_t reserved_32_63:32;
208 uint64_t reserved_3_63:61;
[all …]
Dcvmx-asxx-defs.h7 * Copyright (C) 2003-2018 Cavium, Inc.
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
383 uint64_t reserved_3_63:61;
387 uint64_t reserved_3_63:61;
435 uint64_t reserved_32_63:32;
436 uint64_t sig:32;
438 uint64_t sig:32;
439 uint64_t reserved_32_63:32;
535 uint64_t reserved_3_63:61;
[all …]
/linux-6.12.1/drivers/staging/media/rkvdec/
Drkvdec-h264.c1 // SPDX-License-Identifier: GPL-2.0
9 * Jeffy Chen <jeffy.chen@rock-chips.com>
12 #include <media/v4l2-h264.h>
13 #include <media/v4l2-mem2mem.h>
16 #include "rkvdec-regs.h"
83 #define SCALING_LIST_ADDRESS PS_FIELD(184, 32)
86 #define DPB_OFFS(i, j) (288 + ((j) * 32 * 7) + ((i) * 7))
133 /* Table 9-12 – Values of variables m and n for ctxIdx from 0 to 10 */
134 CABAC_ENTRY(0, 20, -15, 20, -15, 20, -15, 20, -15),
137 CABAC_ENTRY(3, 20, -15, 20, -15, 20, -15, 20, -15),
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/linux-6.12.1/drivers/mmc/host/
Dcavium.h8 * Copyright (C) 2012-2017 Cavium Inc.
26 #define MIO_EMM_DMA_FIFO_CFG(x) (0x00 + x->reg_off_dma)
27 #define MIO_EMM_DMA_FIFO_ADR(x) (0x10 + x->reg_off_dma)
28 #define MIO_EMM_DMA_FIFO_CMD(x) (0x18 + x->reg_off_dma)
29 #define MIO_EMM_DMA_CFG(x) (0x20 + x->reg_off_dma)
30 #define MIO_EMM_DMA_ADR(x) (0x28 + x->reg_off_dma)
31 #define MIO_EMM_DMA_INT(x) (0x30 + x->reg_off_dma)
32 #define MIO_EMM_DMA_INT_W1S(x) (0x38 + x->reg_off_dma)
33 #define MIO_EMM_DMA_INT_ENA_W1S(x) (0x40 + x->reg_off_dma)
34 #define MIO_EMM_DMA_INT_ENA_W1C(x) (0x48 + x->reg_off_dma)
[all …]
/linux-6.12.1/arch/powerpc/kernel/
Dcpu_setup_ppc970.S1 /* SPDX-License-Identifier: GPL-2.0-or-later */
11 #include <asm/asm-offsets.h>
21 * pages are enabled with HID4:61 and clear HID5:DCBZ_size and
27 rldimi r3,r0,2,61 /* clear bit 61 (lg_pg_en) */
41 li r3,0x1200 /* enable i-fetch cacheability */
60 #define CS_SIZE 32
80 rldimi r0,r11,32,31 /* clear EN_ATTN */
94 rldimi r0,r11,32,31 /* clear EN_ATTN */
/linux-6.12.1/mm/damon/tests/
Dvaddr-kunit.h1 /* SPDX-License-Identifier: GPL-2.0 */
20 int i, ret = -ENOMEM; in __link_vmas()
28 mas_set_range(&mas, vmas[i].vm_start, vmas[i].vm_end - 1); in __link_vmas()
47 * heap and the mmap()-ed regions, and 2) the mmap()-ed regions and stack.
57 * For example, suppose virtual address ranges of 10-20, 20-25, 200-210,
58 * 210-220, 300-305, and 307-330 (Other comments represent this mappings in
59 * more short form: 10-20-25, 200-210-220, 300-305, 307-330) of a process are
61 * and end with 305. The process also has three unmapped areas, 25-200,
62 * 220-300, and 305-307. Among those, 25-200 and 220-300 are the biggest two
63 * unmapped areas, and thus it should be converted to three regions of 10-25,
[all …]
/linux-6.12.1/drivers/media/v4l2-core/
Dv4l2-vp9.c1 // SPDX-License-Identifier: GPL-2.0
12 #include <media/v4l2-vp9.h>
19 { 73, 32, 19, 187, 222, 215, 46, 34, 100 }, /*left = h */
20 { 91, 30, 32, 116, 121, 186, 93, 86, 94 }, /*left = d45 */
25 { 74, 32, 27, 107, 86, 160, 63, 134, 102 }, /*left = d63 */
33 { 38, 32, 85, 140, 46, 112, 54, 151, 133 }, /*left = d117*/
34 { 39, 27, 61, 131, 110, 175, 44, 75, 136 }, /*left = d153*/
37 { 36, 61, 116, 114, 128, 162, 80, 125, 82 }, /*left = tm */
39 { 82, 26, 26, 171, 208, 204, 44, 32, 105 }, /*left = dc */
54 { 60, 32, 33, 112, 71, 220, 64, 89, 104 }, /*left = d135*/
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/linux-6.12.1/arch/x86/crypto/
Dsha512-avx2-asm.S2 # Implement fast SHA-512 with AVX2 instructions. (x86_64)
22 # - Redistributions of source code must retain the above
26 # - Redistributions in binary form must reproduce the above
42 # This code is described in an Intel White-Paper:
43 # "Fast SHA-512 Implementations on Intel Architecture Processors"
118 # Add reg to mem using reg-mem add and store
166 # Extract w[t-7]
167 MY_VPALIGNR YTMP0, Y_3, Y_2, 8 # YTMP0 = W[-7]
168 # Calculate w[t-16] + w[t-7]
169 vpaddq Y_0, YTMP0, YTMP0 # YTMP0 = W[-7] + W[-16]
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/linux-6.12.1/arch/parisc/kernel/vdso64/
Dsigtramp.S1 /* SPDX-License-Identifier: GPL-2.0 */
6 * Copyright (C) 2018-2022 Helge Deller <deller@gmx.de>
11 #include <generated/asm-offsets.h>
16 a 64-byte boundary by 0, 4 or 5 instructions. Since the vdso trampoline
43 .Lsigrt_start = . - 4
56 .size __kernel_sigtramp_rt,.-__kernel_sigtramp_rt
61 #define PTREGS SIGFRAME_CONTEXT_REGS /* 64-bit process offset is -720 */
71 .long .Lcie_end - .Lcie_start
75 .stringz "zRS" /* NUL-terminated augmentation string */
78 .byte 61 /* Return address register column, iaoq[0] */
[all …]
/linux-6.12.1/include/dt-bindings/clock/
Dr9a08g045-cpg.h1 /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
8 #include <dt-bindings/clock/renesas-cpg-mssr.h>
70 #define R9A08G045_POEG_C_CLKP 32
99 #define R9A08G045_SSI2_PCLK_SFR 61
179 #define R9A08G045_POEG_A_RST 32
208 #define R9A08G045_SCIF2_RST_SYSTEM_N 61
275 #define R9A08G045_PD_USB0 32
304 #define R9A08G045_PD_SPDIF 61
Dexynos5433.h1 /* SPDX-License-Identifier: GPL-2.0 */
36 #define CLK_MOUT_SCLK_MMC2_A 32
65 #define CLK_MOUT_SCLK_SPDIF 61
233 #define CLK_MOUT_SCLK_DECON_ECLK_B 32
257 #define CLK_DIV_ACLK_MIF_133 61
427 #define CLK_SCLK_SPI1 32
456 #define CLK_SCLK_IOCLK_SPI0 61
497 #define CLK_PCLK_OTP_CON_APBIF 32
540 #define CLK_PHYCLK_USBHOST20_PHY_HSIC1_PHY 32
558 #define CLK_SCLK_MMC2 61
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Dgoogle,gs101.h1 /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
46 #define CLK_MOUT_CMU_DNS_BUS 32
75 #define CLK_MOUT_CMU_MIF_SWITCH 61
275 #define CLK_GOUT_APM_LHS_AXI_G_DBGCORE_I_CLK 32
304 #define CLK_GOUT_APM_UASC_G_SWD_ACLK 61
348 #define CLK_GOUT_HSI0_CLK_HSI0_BUS_CLK 32
402 #define CLK_GOUT_HSI2_PPMU_HSI2_ACLK 32
464 #define CLK_GOUT_MISC_PPMU_MISC_PCLK 32
493 #define CLK_GOUT_MISC_SSMT_SPDMA_ACLK 61
540 #define CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_1 32
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/linux-6.12.1/drivers/clk/rockchip/
Drst-rk3576.c1 // SPDX-License-Identifier: GPL-2.0-or-later
11 #include <dt-bindings/reset/rockchip,rk3576-cru.h>
294 RK3576_CRU_RESET_OFFSET(SRST_A_RKNN_CBUF, 32, 0),
295 RK3576_CRU_RESET_OFFSET(SRST_A_RVCORE0, 32, 1),
296 RK3576_CRU_RESET_OFFSET(SRST_P_NPU_GRF, 32, 2),
297 RK3576_CRU_RESET_OFFSET(SRST_P_PVTPLL_NPU, 32, 3),
298 RK3576_CRU_RESET_OFFSET(SRST_NPU_PVTPLL, 32, 4),
299 RK3576_CRU_RESET_OFFSET(SRST_H_NPU_CM0_BIU, 32, 6),
300 RK3576_CRU_RESET_OFFSET(SRST_F_NPU_CM0_CORE, 32, 7),
301 RK3576_CRU_RESET_OFFSET(SRST_T_NPU_CM0_JTAG, 32, 8),
[all …]
/linux-6.12.1/arch/powerpc/crypto/
Dpoly1305-p10le_64.S1 /* SPDX-License-Identifier: GPL-2.0-or-later */
5 # Copyright 2023- IBM Corp. All rights reserved
10 # Poly1305 - this version mainly using vector/VSX/Scalar
11 # - 26 bits limbs
12 # - Handle multiple 64 byte blcok.
17 # p = 2^130 - 5
25 # 07/22/21 - this revison based on the above sum of products. Setup r^4, r^3, r^2, r and s3, s2, …
50 # k = 32 bytes key
56 #include <asm/asm-offsets.h>
57 #include <asm/asm-compat.h>
[all …]
/linux-6.12.1/drivers/tty/vt/
Ddefkeymap.map1 # SPDX-License-Identifier: GPL-2.0
3 keymaps 0-2,4-5,8,12
5 # keymaps 0-2,4-6,8,12
79 keycode 32 = d
80 altgr keycode 32 = Hex_D
132 keycode 61 = F3 F13 Console_15
133 control keycode 61 = F3
134 alt keycode 61 = Console_3
135 control alt keycode 61 = Console_3
280 string F18 = "\033[32~"
[all …]
/linux-6.12.1/arch/mips/include/asm/sibyte/
Dsb1250_dma.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
33 * Ethernet and Serial DMA Configuration Register 0 (Table 7-4)
75 #define S_DMA_HIGH_WATERMARK _SB_MAKE64(32)
86 * Ethernet and Serial DMA Configuration Register 1 (Table 7-5)
113 #define M_DMA_MBZ2 _SB_MAKEMASK(5, 32)
126 * Ethernet and Serial DMA Descriptor base address (Table 7-6)
133 * ASIC Mode Base Address (Table 7-7)
139 * DMA Descriptor Count Registers (Table 7-8)
146 * Current Descriptor Address Register (Table 7-11)
176 * Descriptor doubleword "A" (Table 7-12)
[all …]
/linux-6.12.1/arch/powerpc/lib/
Dcopy_32.S1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * Memory copy functions for 32-bit PowerPC.
5 * Copyright (C) 1996-2005 Paul Mackerras.
12 #include <asm/code-patching-asm.h>
45 addi r5,r5,-(16 * n); \
48 addi r5,r5,-(16 * n); \
63 CACHELINE_MASK = (L1_CACHE_BYTES-1)
68 addi r6, r3, -4
69 beq- 2f
84 * area is cacheable. -- paulus
[all …]
/linux-6.12.1/tools/perf/util/arm-spe-decoder/
Darm-spe-pkt-decoder.h1 /* SPDX-License-Identifier: GPL-2.0 */
4 * Copyright (c) 2017-2018, Arm Ltd.
15 #define ARM_SPE_NEED_MORE_BYTES -1
16 #define ARM_SPE_BAD_PACKET -2
76 #define SPE_ADDR_PKT_GET_EL(v) (((v) & GENMASK_ULL(62, 61)) >> 61)
142 * the length is rounded up to a power of two and use 32 as one step,
145 * 32 * (2 ^ bits [6:4]) = 32 << (bits [6:4])
147 #define SPE_OP_PKG_SVE_EVL(v) (32 << (((v) & GENMASK_ULL(6, 4)) >> 4))
/linux-6.12.1/drivers/net/ethernet/ibm/ehea/
Dehea_phyp.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
11 * Jan-Bernd Themann <themann@de.ibm.com>
25 * hcp_* - structures, variables and functions releated to Hypervisor Calls
33 #define NEQE_PORTNUM EHEA_BMASK_IBM(32, 47)
45 #define NELR_PORT_MALFUNC EHEA_BMASK_IBM(61, 61)
53 epas->kernel.addr = ioremap((paddr_kernel & PAGE_MASK), PAGE_SIZE) + in hcp_epas_ctor()
55 epas->user.addr = paddr_user; in hcp_epas_ctor()
60 if (epas->kernel.addr) in hcp_epas_dtor()
61 iounmap((void __iomem *)((u64)epas->kernel.addr & PAGE_MASK)); in hcp_epas_dtor()
63 epas->user.addr = 0; in hcp_epas_dtor()
[all …]
/linux-6.12.1/arch/parisc/kernel/vdso32/
Dsigtramp.S1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Signal trampolines for 32 bit processes.
6 * Copyright (C) 2018-2022 Helge Deller <deller@gmx.de>
11 #include <generated/asm-offsets.h>
16 a 64-byte boundary by 0, 4 or 5 instructions. Since the vdso trampoline
43 .Lsigrt_start = . - 4
56 .size __kernel_sigtramp_rt,.-__kernel_sigtramp_rt
62 #define PTREGS SIGFRAME_CONTEXT_REGS32 /* 32-bit process offset is -672 */
72 .long .Lcie_end - .Lcie_start
76 .stringz "zRS" /* NUL-terminated augmentation string */
[all …]

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