mmc/host/cavium.h

8  * Copyright (C) 2012-2017 Cavium Inc.
26 #define MIO_EMM_DMA_FIFO_CFG(x)	(0x00 + x->reg_off_dma)
27 #define MIO_EMM_DMA_FIFO_ADR(x)	(0x10 + x->reg_off_dma)
28 #define MIO_EMM_DMA_FIFO_CMD(x)	(0x18 + x->reg_off_dma)
29 #define MIO_EMM_DMA_CFG(x)	(0x20 + x->reg_off_dma)
30 #define MIO_EMM_DMA_ADR(x)	(0x28 + x->reg_off_dma)
31 #define MIO_EMM_DMA_INT(x)	(0x30 + x->reg_off_dma)
32 #define MIO_EMM_DMA_INT_W1S(x)	(0x38 + x->reg_off_dma)
33 #define MIO_EMM_DMA_INT_ENA_W1S(x) (0x40 + x->reg_off_dma)
34 #define MIO_EMM_DMA_INT_ENA_W1C(x) (0x48 + x->reg_off_dma)
37 #define MIO_EMM_CFG(x)		(0x00 + x->reg_off)
38 #define MIO_EMM_SWITCH(x)	(0x48 + x->reg_off)
39 #define MIO_EMM_DMA(x)		(0x50 + x->reg_off)
40 #define MIO_EMM_CMD(x)		(0x58 + x->reg_off)
41 #define MIO_EMM_RSP_STS(x)	(0x60 + x->reg_off)
42 #define MIO_EMM_RSP_LO(x)	(0x68 + x->reg_off)
43 #define MIO_EMM_RSP_HI(x)	(0x70 + x->reg_off)
44 #define MIO_EMM_INT(x)		(0x78 + x->reg_off)
45 #define MIO_EMM_INT_EN(x)	(0x80 + x->reg_off)
46 #define MIO_EMM_WDOG(x)		(0x88 + x->reg_off)
47 #define MIO_EMM_SAMPLE(x)	(0x90 + x->reg_off)
48 #define MIO_EMM_STS_MASK(x)	(0x98 + x->reg_off)
49 #define MIO_EMM_RCA(x)		(0xa0 + x->reg_off)
50 #define MIO_EMM_INT_EN_SET(x)	(0xb0 + x->reg_off)
51 #define MIO_EMM_INT_EN_CLR(x)	(0xb8 + x->reg_off)
52 #define MIO_EMM_BUF_IDX(x)	(0xe0 + x->reg_off)
53 #define MIO_EMM_BUF_DAT(x)	(0xe8 + x->reg_off)
95 	struct mmc_host *mmc;		/* slot-level mmc_core object */
133 #define MIO_EMM_CMD_BUS_ID		GENMASK_ULL(61, 60)
139 #define MIO_EMM_CMD_IDX			GENMASK_ULL(37, 32)
143 #define MIO_EMM_DMA_BUS_ID		GENMASK_ULL(61, 60)
151 #define MIO_EMM_DMA_BLOCK_CNT		GENMASK_ULL(47, 32)
156 #define MIO_EMM_DMA_CFG_CLR		BIT_ULL(61)
172 #define MIO_EMM_RSP_STS_BUS_ID		GENMASK_ULL(61, 60)
198 #define MIO_EMM_SWITCH_BUS_ID		GENMASK_ULL(61, 60)
205 #define MIO_EMM_SWITCH_POWER_CLASS	GENMASK_ULL(35, 32)