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/linux-6.12.1/Documentation/devicetree/bindings/interrupt-controller/
Darm,gic-v3.yaml33 enum: [ 0, 1, 2 ]
35 enum: [ 1, 2 ]
47 interrupts, 2 for interrupts in the Extended SPI range, 3 for the
50 The 2nd cell contains the interrupt number for the interrupt type.
86 minItems: 2
127 minItems: 2
128 maxItems: 2
138 maxItems: 2
227 minItems: 2
228 maxItems: 2
[all …]
/linux-6.12.1/arch/arm64/boot/dts/ti/
Dk3-j784s4-evm-usxgmii-exp1-exp2.dtso4 * and ENET-2 Expansion slots of J784S4 EVM.
21 ethernet2 = "/bus@100000/ethernet@c000000/ethernet-ports/port@2";
22 ethernet3 = "/bus@100000/ethernet@c200000/ethernet-ports/port@1";
46 phys = <&cpsw0_phy_gmii_sel 2>, <&serdes2_usxgmii_link>;
65 serdes2_usxgmii_link: phy@2 {
66 reg = <2>;
67 cdns,num-lanes = <2>;
Dk3-j784s4-evm-quad-port-eth-exp1.dtso30 ethernet5 = "/bus@100000/ethernet@c200000/ethernet-ports/port@1";
141 reg = <2>;
Dk3-j721s2-main.dtsi100 clocks = <&ehrpwm_tbclk 2>, <&k3_clks 162 0>;
137 #address-cells = <2>;
138 #size-cells = <2>;
203 #address-cells = <2>;
204 #size-cells = <2>;
225 assigned-clock-parents = <&k3_clks 63 2>;
237 assigned-clock-parents = <&k3_clks 64 2>;
249 assigned-clock-parents = <&k3_clks 65 2>;
261 assigned-clock-parents = <&k3_clks 66 2>;
273 assigned-clock-parents = <&k3_clks 67 2>;
[all …]
Dk3-j784s4-main.dtsi158 clocks = <&ehrpwm_tbclk 2>, <&k3_clks 221 0>;
197 #address-cells = <2>;
198 #size-cells = <2>;
263 #address-cells = <2>;
264 #size-cells = <2>;
282 clocks = <&k3_clks 97 2>;
284 assigned-clocks = <&k3_clks 97 2>;
294 clocks = <&k3_clks 98 2>;
296 assigned-clocks = <&k3_clks 98 2>;
306 clocks = <&k3_clks 99 2>;
[all …]
/linux-6.12.1/arch/arm64/boot/dts/qcom/
Dqcs8550.dtsi12 #address-cells = <2>;
13 #size-cells = <2>;
27 * 2. Firmware related memory regions which are shared with Kernel
132 cvp_mem: cvp-region@9c200000 {
Dmsm8976.dtsi18 #address-cells = <2>;
19 #size-cells = <2>;
42 #cooling-cells = <2>;
53 #cooling-cells = <2>;
56 CPU2: cpu@2 {
64 #cooling-cells = <2>;
75 #cooling-cells = <2>;
86 #cooling-cells = <2>;
97 #cooling-cells = <2>;
108 #cooling-cells = <2>;
[all …]
Dmsm8953.dtsi17 #address-cells = <2>;
18 #size-cells = <2>;
48 #cooling-cells = <2>;
58 #cooling-cells = <2>;
61 CPU2: cpu@2 {
68 #cooling-cells = <2>;
78 #cooling-cells = <2>;
88 #cooling-cells = <2>;
98 #cooling-cells = <2>;
108 #cooling-cells = <2>;
[all …]
Dsdm630.dtsi22 #address-cells = <2>;
23 #size-cells = <2>;
49 #address-cells = <2>;
63 #cooling-cells = <2>;
67 cache-level = <2>;
83 #cooling-cells = <2>;
98 #cooling-cells = <2>;
113 #cooling-cells = <2>;
128 #cooling-cells = <2>;
132 cache-level = <2>;
[all …]
Dsm8550.dtsi30 #address-cells = <2>;
31 #size-cells = <2>;
51 clock-div = <2>;
59 clock-div = <2>;
64 #address-cells = <2>;
79 #cooling-cells = <2>;
82 cache-level = <2>;
105 #cooling-cells = <2>;
108 cache-level = <2>;
126 #cooling-cells = <2>;
[all …]
/linux-6.12.1/arch/arm/boot/dts/samsung/
Ds3c64xx.dtsi62 sdhci0: mmc@7c200000 {
67 clock-names = "hsmmc", "mmc_busclk.0", "mmc_busclk.2";
78 clock-names = "hsmmc", "mmc_busclk.0", "mmc_busclk.2";
89 clock-names = "hsmmc", "mmc_busclk.0", "mmc_busclk.2";
/linux-6.12.1/arch/arm64/boot/dts/apm/
Dapm-shadowcat.dtsi11 #address-cells = <2>;
12 #size-cells = <2>;
15 #address-cells = <2>;
100 cache-level = <2>;
105 cache-level = <2>;
108 xgene_L2_2: l2-cache-2 {
110 cache-level = <2>;
115 cache-level = <2>;
123 #address-cells = <2>;
124 #size-cells = <2>;
[all …]
Dapm-storm.dtsi11 #address-cells = <2>;
12 #size-cells = <2>;
15 #address-cells = <2>;
84 cache-level = <2>;
89 cache-level = <2>;
92 xgene_L2_2: l2-cache-2 {
94 cache-level = <2>;
99 cache-level = <2>;
138 #address-cells = <2>;
139 #size-cells = <2>;
[all …]
/linux-6.12.1/arch/arm64/boot/dts/freescale/
Dfsl-ls208xa.dtsi19 #address-cells = <2>;
20 #size-cells = <2>;
39 /* DRAM space - 1, size : 2 GB DRAM */
57 #address-cells = <2>;
58 #size-cells = <2>;
100 thermal-sensors = <&tmu 2>;
257 #address-cells = <2>;
258 #size-cells = <2>;
265 #clock-cells = <2>;
293 #interrupt-cells = <2>;
[all …]
Dimx93.dtsi18 #address-cells = <2>;
19 #size-cells = <2>;
70 #cooling-cells = <2>;
86 #cooling-cells = <2>;
102 cache-level = <2>;
112 cache-level = <2>;
150 interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
264 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, // 2: Reserved
307 #mbox-cells = <2>;
677 #mbox-cells = <2>;
[all …]