1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * Copyright (c) 2016-2022, AngeloGioacchino Del Regno 4 * <angelogioacchino.delregno@collabora.com> 5 * Copyright (c) 2022, Konrad Dybcio <konrad.dybcio@somainline.org> 6 * Copyright (c) 2022, Marijn Suijten <marijn.suijten@somainline.org> 7 */ 8 9#include <dt-bindings/clock/qcom,gcc-msm8976.h> 10#include <dt-bindings/clock/qcom,rpmcc.h> 11#include <dt-bindings/gpio/gpio.h> 12#include <dt-bindings/interrupt-controller/arm-gic.h> 13#include <dt-bindings/interrupt-controller/irq.h> 14#include <dt-bindings/power/qcom-rpmpd.h> 15 16/ { 17 interrupt-parent = <&intc>; 18 #address-cells = <2>; 19 #size-cells = <2>; 20 21 chosen { }; 22 23 clocks { 24 xo_board: xo-board { 25 compatible = "fixed-clock"; 26 #clock-cells = <0>; 27 }; 28 }; 29 30 cpus { 31 #address-cells = <1>; 32 #size-cells = <0>; 33 34 CPU0: cpu@0 { 35 device_type = "cpu"; 36 compatible = "arm,cortex-a53"; 37 reg = <0x0>; 38 enable-method = "psci"; 39 cpu-idle-states = <&little_cpu_sleep_0>; 40 capacity-dmips-mhz = <573>; 41 next-level-cache = <&l2_0>; 42 #cooling-cells = <2>; 43 }; 44 45 CPU1: cpu@1 { 46 device_type = "cpu"; 47 compatible = "arm,cortex-a53"; 48 reg = <0x1>; 49 enable-method = "psci"; 50 cpu-idle-states = <&little_cpu_sleep_0>; 51 capacity-dmips-mhz = <573>; 52 next-level-cache = <&l2_0>; 53 #cooling-cells = <2>; 54 }; 55 56 CPU2: cpu@2 { 57 device_type = "cpu"; 58 compatible = "arm,cortex-a53"; 59 reg = <0x2>; 60 enable-method = "psci"; 61 cpu-idle-states = <&little_cpu_sleep_0>; 62 capacity-dmips-mhz = <573>; 63 next-level-cache = <&l2_0>; 64 #cooling-cells = <2>; 65 }; 66 67 CPU3: cpu@3 { 68 device_type = "cpu"; 69 compatible = "arm,cortex-a53"; 70 reg = <0x3>; 71 enable-method = "psci"; 72 cpu-idle-states = <&little_cpu_sleep_0>; 73 capacity-dmips-mhz = <573>; 74 next-level-cache = <&l2_0>; 75 #cooling-cells = <2>; 76 }; 77 78 CPU4: cpu@100 { 79 device_type = "cpu"; 80 compatible = "arm,cortex-a72"; 81 reg = <0x100>; 82 enable-method = "psci"; 83 cpu-idle-states = <&big_cpu_sleep_0 &big_cpu_sleep_1>; 84 capacity-dmips-mhz = <1024>; 85 next-level-cache = <&l2_1>; 86 #cooling-cells = <2>; 87 }; 88 89 CPU5: cpu@101 { 90 device_type = "cpu"; 91 compatible = "arm,cortex-a72"; 92 reg = <0x101>; 93 enable-method = "psci"; 94 cpu-idle-states = <&big_cpu_sleep_0 &big_cpu_sleep_1>; 95 capacity-dmips-mhz = <1024>; 96 next-level-cache = <&l2_1>; 97 #cooling-cells = <2>; 98 }; 99 100 CPU6: cpu@102 { 101 device_type = "cpu"; 102 compatible = "arm,cortex-a72"; 103 reg = <0x102>; 104 enable-method = "psci"; 105 cpu-idle-states = <&big_cpu_sleep_0 &big_cpu_sleep_1>; 106 capacity-dmips-mhz = <1024>; 107 next-level-cache = <&l2_1>; 108 #cooling-cells = <2>; 109 }; 110 111 CPU7: cpu@103 { 112 device_type = "cpu"; 113 compatible = "arm,cortex-a72"; 114 reg = <0x103>; 115 enable-method = "psci"; 116 cpu-idle-states = <&big_cpu_sleep_0 &big_cpu_sleep_1>; 117 capacity-dmips-mhz = <1024>; 118 next-level-cache = <&l2_1>; 119 #cooling-cells = <2>; 120 }; 121 122 cpu-map { 123 cluster0 { 124 core0 { 125 cpu = <&CPU0>; 126 }; 127 128 core1 { 129 cpu = <&CPU1>; 130 }; 131 132 core2 { 133 cpu = <&CPU2>; 134 }; 135 136 core3 { 137 cpu = <&CPU3>; 138 }; 139 }; 140 141 cluster1 { 142 core0 { 143 cpu = <&CPU4>; 144 }; 145 146 core1 { 147 cpu = <&CPU5>; 148 }; 149 150 core2 { 151 cpu = <&CPU6>; 152 }; 153 154 core3 { 155 cpu = <&CPU7>; 156 }; 157 }; 158 }; 159 160 idle-states { 161 entry-method = "psci"; 162 163 little_cpu_sleep_0: cpu-sleep-0-0 { 164 compatible = "arm,idle-state"; 165 idle-state-name = "little-power-collapse"; 166 arm,psci-suspend-param = <0x40000003>; 167 entry-latency-us = <181>; 168 exit-latency-us = <149>; 169 min-residency-us = <703>; 170 local-timer-stop; 171 }; 172 173 big_cpu_sleep_0: cpu-sleep-1-0 { 174 compatible = "arm,idle-state"; 175 idle-state-name = "big-retention"; 176 arm,psci-suspend-param = <0x00000002>; 177 entry-latency-us = <142>; 178 exit-latency-us = <99>; 179 min-residency-us = <242>; 180 }; 181 182 big_cpu_sleep_1: cpu-sleep-1-1 { 183 compatible = "arm,idle-state"; 184 idle-state-name = "big-power-collapse"; 185 arm,psci-suspend-param = <0x40000003>; 186 entry-latency-us = <158>; 187 exit-latency-us = <144>; 188 min-residency-us = <863>; 189 local-timer-stop; 190 }; 191 }; 192 193 l2_0: l2-cache0 { 194 compatible = "cache"; 195 cache-level = <2>; 196 cache-unified; 197 }; 198 199 l2_1: l2-cache1 { 200 compatible = "cache"; 201 cache-level = <2>; 202 cache-unified; 203 }; 204 }; 205 206 firmware { 207 scm: scm { 208 compatible = "qcom,scm-msm8976", "qcom,scm"; 209 clocks = <&gcc GCC_CRYPTO_CLK>, 210 <&gcc GCC_CRYPTO_AXI_CLK>, 211 <&gcc GCC_CRYPTO_AHB_CLK>; 212 clock-names = "core", "bus", "iface"; 213 #reset-cells = <1>; 214 215 qcom,dload-mode = <&tcsr 0x6100>; 216 }; 217 }; 218 219 memory@80000000 { 220 device_type = "memory"; 221 /* We expect the bootloader to fill in the size */ 222 reg = <0x0 0x80000000 0x0 0x0>; 223 }; 224 225 pmu-a53 { 226 compatible = "arm,cortex-a53-pmu"; 227 interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 228 }; 229 230 pmu_a72: pmu-a72 { 231 compatible = "arm,cortex-a72-pmu"; 232 interrupts = <GIC_PPI 7 (GIC_CPU_MASK_RAW(0xf0) | IRQ_TYPE_LEVEL_HIGH)>; 233 }; 234 235 236 psci { 237 compatible = "arm,psci-1.0"; 238 method = "smc"; 239 }; 240 241 rpm: remoteproc { 242 compatible = "qcom,msm8976-rpm-proc", "qcom,rpm-proc"; 243 244 smd-edge { 245 interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>; 246 mboxes = <&apcs 0>; 247 qcom,smd-edge = <15>; 248 249 rpm_requests: rpm-requests { 250 compatible = "qcom,rpm-msm8976", "qcom,smd-rpm"; 251 qcom,smd-channels = "rpm_requests"; 252 253 rpmcc: clock-controller { 254 compatible = "qcom,rpmcc-msm8976", "qcom,rpmcc"; 255 clocks = <&xo_board>; 256 clock-names = "xo"; 257 #clock-cells = <1>; 258 }; 259 260 rpmpd: power-controller { 261 compatible = "qcom,msm8976-rpmpd"; 262 #power-domain-cells = <1>; 263 operating-points-v2 = <&rpmpd_opp_table>; 264 265 rpmpd_opp_table: opp-table { 266 compatible = "operating-points-v2"; 267 268 rpmpd_opp_ret: opp1 { 269 opp-level = <RPM_SMD_LEVEL_RETENTION>; 270 }; 271 272 rpmpd_opp_ret_plus: opp2 { 273 opp-level = <RPM_SMD_LEVEL_RETENTION_PLUS>; 274 }; 275 276 rpmpd_opp_min_svs: opp3 { 277 opp-level = <RPM_SMD_LEVEL_MIN_SVS>; 278 }; 279 280 rpmpd_opp_low_svs: opp4 { 281 opp-level = <RPM_SMD_LEVEL_LOW_SVS>; 282 }; 283 284 rpmpd_opp_svs: opp5 { 285 opp-level = <RPM_SMD_LEVEL_SVS>; 286 }; 287 288 rpmpd_opp_svs_plus: opp6 { 289 opp-level = <RPM_SMD_LEVEL_SVS_PLUS>; 290 }; 291 292 rpmpd_opp_nom: opp7 { 293 opp-level = <RPM_SMD_LEVEL_NOM>; 294 }; 295 296 rpmpd_opp_nom_plus: opp8 { 297 opp-level = <RPM_SMD_LEVEL_NOM_PLUS>; 298 }; 299 300 rpmpd_opp_turbo: opp9 { 301 opp-level = <RPM_SMD_LEVEL_TURBO>; 302 }; 303 304 rpmpd_opp_turbo_no_cpr: opp10 { 305 opp-level = <RPM_SMD_LEVEL_TURBO_NO_CPR>; 306 }; 307 308 rpmpd_opp_turbo_high: opp111 { 309 opp-level = <RPM_SMD_LEVEL_TURBO_HIGH>; 310 }; 311 }; 312 }; 313 }; 314 }; 315 }; 316 317 reserved-memory { 318 #address-cells = <2>; 319 #size-cells = <2>; 320 ranges; 321 322 ext-region@85b00000 { 323 reg = <0x0 0x85b00000 0x0 0x500000>; 324 no-map; 325 }; 326 327 smem@86300000 { 328 compatible = "qcom,smem"; 329 reg = <0x0 0x86300000 0x0 0x100000>; 330 no-map; 331 332 hwlocks = <&tcsr_mutex 3>; 333 qcom,rpm-msg-ram = <&rpm_msg_ram>; 334 }; 335 336 reserved@86400000 { 337 reg = <0x0 0x86400000 0x0 0x800000>; 338 no-map; 339 }; 340 341 mpss_mem: mpss@86c00000 { 342 reg = <0x0 0x86c00000 0x0 0x5600000>; 343 no-map; 344 }; 345 346 lpass_mem: lpass@8c200000 { 347 reg = <0x0 0x8c200000 0x0 0x1000000>; 348 no-map; 349 }; 350 351 wcnss_fw_mem: wcnss@8d200000 { 352 reg = <0x0 0x8d200000 0x0 0x800000>; 353 no-map; 354 }; 355 356 venus_mem: memory@8da00000 { 357 reg = <0x0 0x8da00000 0x0 0x2600000>; 358 no-map; 359 }; 360 361 tz-apps@8dd00000 { 362 reg = <0x0 0x8dd00000 0x0 0x1400000>; 363 no-map; 364 }; 365 }; 366 367 smp2p-hexagon { 368 compatible = "qcom,smp2p"; 369 interrupts = <GIC_SPI 291 IRQ_TYPE_EDGE_RISING>; 370 mboxes = <&apcs 10>; 371 372 qcom,local-pid = <0>; 373 qcom,remote-pid = <2>; 374 qcom,smem = <443>, <429>; 375 376 adsp_smp2p_out: master-kernel { 377 qcom,entry-name = "master-kernel"; 378 379 #qcom,smem-state-cells = <1>; 380 }; 381 382 adsp_smp2p_in: slave-kernel { 383 qcom,entry-name = "slave-kernel"; 384 385 interrupt-controller; 386 #interrupt-cells = <2>; 387 }; 388 }; 389 390 smp2p-modem { 391 compatible = "qcom,smp2p"; 392 interrupts = <GIC_SPI 27 IRQ_TYPE_EDGE_RISING>; 393 mboxes = <&apcs 14>; 394 395 qcom,local-pid = <0>; 396 qcom,remote-pid = <1>; 397 qcom,smem = <435>, <428>; 398 399 modem_smp2p_out: master-kernel { 400 qcom,entry-name = "master-kernel"; 401 402 #qcom,smem-state-cells = <1>; 403 }; 404 405 modem_smp2p_in: slave-kernel { 406 qcom,entry-name = "slave-kernel"; 407 408 interrupt-controller; 409 #interrupt-cells = <2>; 410 }; 411 }; 412 413 smp2p-wcnss { 414 compatible = "qcom,smp2p"; 415 interrupts = <GIC_SPI 143 IRQ_TYPE_EDGE_RISING>; 416 mboxes = <&apcs 18>; 417 418 qcom,local-pid = <0>; 419 qcom,remote-pid = <4>; 420 qcom,smem = <451>, <431>; 421 422 wcnss_smp2p_out: master-kernel { 423 qcom,entry-name = "master-kernel"; 424 425 #qcom,smem-state-cells = <1>; 426 }; 427 428 wcnss_smp2p_in: slave-kernel { 429 qcom,entry-name = "slave-kernel"; 430 431 interrupt-controller; 432 #interrupt-cells = <2>; 433 }; 434 }; 435 436 smsm { 437 compatible = "qcom,smsm"; 438 439 #address-cells = <1>; 440 #size-cells = <0>; 441 442 mboxes = <0>, <&apcs 13>, <&apcs 9>, <&apcs 19>; 443 444 apps_smsm: apps@0 { 445 reg = <0>; 446 #qcom,smem-state-cells = <1>; 447 }; 448 449 hexagon_smsm: hexagon@1 { 450 reg = <1>; 451 interrupts = <GIC_SPI 290 IRQ_TYPE_EDGE_RISING>; 452 453 interrupt-controller; 454 #interrupt-cells = <2>; 455 }; 456 457 wcnss_smsm: wcnss@6 { 458 reg = <6>; 459 interrupts = <GIC_SPI 144 IRQ_TYPE_EDGE_RISING>; 460 461 interrupt-controller; 462 #interrupt-cells = <2>; 463 }; 464 }; 465 466 soc: soc@0 { 467 #address-cells = <1>; 468 #size-cells = <1>; 469 ranges = <0 0 0 0xffffffff>; 470 compatible = "simple-bus"; 471 472 rng@22000 { 473 compatible = "qcom,prng"; 474 reg = <0x00022000 0x140>; 475 clocks = <&gcc GCC_PRNG_AHB_CLK>; 476 clock-names = "core"; 477 }; 478 479 rpm_msg_ram: sram@60000 { 480 compatible = "qcom,rpm-msg-ram"; 481 reg = <0x00060000 0x8000>; 482 }; 483 484 usb_hs_phy: phy@6c000 { 485 compatible = "qcom,usb-hs-28nm-femtophy"; 486 reg = <0x0006c000 0x200>; 487 #phy-cells = <0>; 488 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, 489 <&gcc GCC_USB_HS_PHY_CFG_AHB_CLK>, 490 <&gcc GCC_USB2A_PHY_SLEEP_CLK>; 491 clock-names = "ref", "ahb", "sleep"; 492 resets = <&gcc RST_QUSB2_PHY_BCR>, 493 <&gcc RST_USB2_HS_PHY_ONLY_BCR>; 494 reset-names = "phy", "por"; 495 status = "disabled"; 496 }; 497 498 qfprom: qfprom@a4000 { 499 compatible = "qcom,msm8976-qfprom", "qcom,qfprom"; 500 reg = <0x000a4000 0x1000>; 501 #address-cells = <1>; 502 #size-cells = <1>; 503 504 tsens_base1: base1@218 { 505 reg = <0x218 1>; 506 bits = <0 8>; 507 }; 508 509 tsens_s0_p1: s0-p1@219 { 510 reg = <0x219 0x1>; 511 bits = <0 6>; 512 }; 513 514 tsens_s0_p2: s0-p2@219 { 515 reg = <0x219 0x2>; 516 bits = <6 6>; 517 }; 518 519 tsens_s1_p1: s1-p1@21a { 520 reg = <0x21a 0x2>; 521 bits = <4 6>; 522 }; 523 524 tsens_s1_p2: s1-p2@21b { 525 reg = <0x21b 0x1>; 526 bits = <2 6>; 527 }; 528 529 tsens_s2_p1: s2-p1@21c { 530 reg = <0x21c 0x1>; 531 bits = <0 6>; 532 }; 533 534 tsens_s2_p2: s2-p2@21c { 535 reg = <0x21c 0x2>; 536 bits = <6 6>; 537 }; 538 539 tsens_s3_p1: s3-p1@21d { 540 reg = <0x21d 0x2>; 541 bits = <4 6>; 542 }; 543 544 tsens_s3_p2: s3-p2@21e { 545 reg = <0x21e 0x1>; 546 bits = <2 6>; 547 }; 548 549 tsens_base2: base2@220 { 550 reg = <0x220 1>; 551 bits = <0 8>; 552 }; 553 554 tsens_s4_p1: s4-p1@221 { 555 reg = <0x221 0x1>; 556 bits = <0 6>; 557 }; 558 559 tsens_s4_p2: s4-p2@221 { 560 reg = <0x221 0x2>; 561 bits = <6 6>; 562 }; 563 564 tsens_s5_p1: s5-p1@222 { 565 reg = <0x222 0x2>; 566 bits = <4 6>; 567 }; 568 569 tsens_s5_p2: s5-p2@223 { 570 reg = <0x224 0x1>; 571 bits = <2 6>; 572 }; 573 574 tsens_s6_p1: s6-p1@224 { 575 reg = <0x224 0x1>; 576 bits = <0 6>; 577 }; 578 579 tsens_s6_p2: s6-p2@224 { 580 reg = <0x224 0x2>; 581 bits = <6 6>; 582 }; 583 584 tsens_s7_p1: s7-p1@225 { 585 reg = <0x225 0x2>; 586 bits = <4 6>; 587 }; 588 589 tsens_s7_p2: s7-p2@226 { 590 reg = <0x226 0x2>; 591 bits = <2 6>; 592 }; 593 594 tsens_mode: mode@228 { 595 reg = <0x228 1>; 596 bits = <0 3>; 597 }; 598 599 tsens_s8_p1: s8-p1@228 { 600 reg = <0x228 0x2>; 601 bits = <3 6>; 602 }; 603 604 tsens_s8_p2: s8-p2@229 { 605 reg = <0x229 0x1>; 606 bits = <1 6>; 607 }; 608 609 tsens_s9_p1: s9-p1@229 { 610 reg = <0x229 0x2>; 611 bits = <7 6>; 612 }; 613 614 tsens_s9_p2: s9-p2@22a { 615 reg = <0x22a 0x2>; 616 bits = <5 6>; 617 }; 618 619 tsens_s10_p1: s10-p1@22b { 620 reg = <0x22b 0x2>; 621 bits = <3 6>; 622 }; 623 624 tsens_s10_p2: s10-p2@22c { 625 reg = <0x22c 0x1>; 626 bits = <1 6>; 627 }; 628 }; 629 630 tsens: thermal-sensor@4a9000 { 631 compatible = "qcom,msm8976-tsens", "qcom,tsens-v1"; 632 reg = <0x004a9000 0x1000>, /* TM */ 633 <0x004a8000 0x1000>; /* SROT */ 634 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; 635 interrupt-names = "uplow"; 636 nvmem-cells = <&tsens_mode>, 637 <&tsens_base1>, <&tsens_base2>, 638 <&tsens_s0_p1>, <&tsens_s0_p2>, 639 <&tsens_s1_p1>, <&tsens_s1_p2>, 640 <&tsens_s2_p1>, <&tsens_s2_p2>, 641 <&tsens_s3_p1>, <&tsens_s3_p2>, 642 <&tsens_s4_p1>, <&tsens_s4_p2>, 643 <&tsens_s5_p1>, <&tsens_s5_p2>, 644 <&tsens_s6_p1>, <&tsens_s6_p2>, 645 <&tsens_s7_p1>, <&tsens_s7_p2>, 646 <&tsens_s8_p1>, <&tsens_s8_p2>, 647 <&tsens_s9_p1>, <&tsens_s9_p2>, 648 <&tsens_s10_p1>, <&tsens_s10_p2>; 649 nvmem-cell-names = "mode", 650 "base1", "base2", 651 "s0_p1", "s0_p2", 652 "s1_p1", "s1_p2", 653 "s2_p1", "s2_p2", 654 "s3_p1", "s3_p2", 655 "s4_p1", "s4_p2", 656 "s5_p1", "s5_p2", 657 "s6_p1", "s6_p2", 658 "s7_p1", "s7_p2", 659 "s8_p1", "s8_p2", 660 "s9_p1", "s9_p2", 661 "s10_p1", "s10_p2"; 662 #qcom,sensors = <11>; 663 #thermal-sensor-cells = <1>; 664 }; 665 666 restart@4ab000 { 667 compatible = "qcom,pshold"; 668 reg = <0x004ab000 0x4>; 669 }; 670 671 tlmm: pinctrl@1000000 { 672 compatible = "qcom,msm8976-pinctrl"; 673 reg = <0x01000000 0x300000>; 674 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 675 #gpio-cells = <2>; 676 gpio-controller; 677 gpio-ranges = <&tlmm 0 0 145>; 678 interrupt-controller; 679 #interrupt-cells = <2>; 680 681 spi1_default: spi0-default-state { 682 spi-pins { 683 pins = "gpio0", "gpio1", "gpio3"; 684 function = "blsp_spi1"; 685 drive-strength = <12>; 686 bias-disable; 687 }; 688 689 cs-pins { 690 pins = "gpio2"; 691 function = "blsp_spi1"; 692 drive-strength = <2>; 693 bias-disable; 694 }; 695 }; 696 697 spi1_sleep: spi0-sleep-state { 698 spi-pins { 699 pins = "gpio0", "gpio1", "gpio3"; 700 function = "gpio"; 701 drive-strength = <2>; 702 bias-pull-down; 703 }; 704 705 cs-pins { 706 pins = "gpio2"; 707 function = "gpio"; 708 drive-strength = <2>; 709 bias-disable; 710 }; 711 }; 712 713 blsp1_i2c2_default: blsp1-i2c2-default-state { 714 pins = "gpio6", "gpio7"; 715 function = "blsp_i2c2"; 716 drive-strength = <2>; 717 bias-disable; 718 }; 719 720 blsp1_i2c2_sleep: blsp1-i2c2-sleep-state { 721 pins = "gpio6", "gpio7"; 722 function = "gpio"; 723 drive-strength = <2>; 724 bias-disable; 725 }; 726 727 blsp1_i2c4_default: blsp1-i2c4-default-state { 728 pins = "gpio14", "gpio15"; 729 function = "blsp_i2c4"; 730 drive-strength = <2>; 731 bias-disable; 732 }; 733 734 blsp1_i2c4_sleep: blsp1-i2c4-sleep-state { 735 pins = "gpio14", "gpio15"; 736 function = "gpio"; 737 drive-strength = <2>; 738 bias-disable; 739 }; 740 741 blsp2_uart2_active: blsp2-uart2-active-state { 742 pins = "gpio20", "gpio21"; 743 function = "blsp_uart6"; 744 drive-strength = <4>; 745 bias-disable; 746 }; 747 748 blsp2_uart2_sleep: blsp2-uart2-sleep-state { 749 pins = "gpio20", "gpio21"; 750 function = "gpio"; 751 drive-strength = <2>; 752 bias-disable; 753 }; 754 755 /* 4 (not 6!) interfaces per QUP, BLSP2 indexes are numbered (n)+4 */ 756 blsp2_i2c2_default: blsp2-i2c2-default-state { 757 pins = "gpio22", "gpio23"; 758 function = "blsp_i2c6"; 759 drive-strength = <2>; 760 bias-disable; 761 }; 762 763 blsp2_i2c2_sleep: blsp2-i2c2-sleep-state { 764 pins = "gpio22", "gpio23"; 765 function = "gpio"; 766 drive-strength = <2>; 767 bias-disable; 768 }; 769 770 blsp2_i2c4_default: blsp2-i2c4-default-state { 771 pins = "gpio18", "gpio19"; 772 function = "blsp_i2c8"; 773 drive-strength = <2>; 774 bias-disable; 775 }; 776 777 blsp2_i2c4_sleep: blsp2-i2c4-sleep-state { 778 pins = "gpio18", "gpio19"; 779 function = "gpio"; 780 drive-strength = <2>; 781 bias-disable; 782 }; 783 784 wcss_wlan_default: wcss-wlan-default-state { 785 wcss-wlan2-pins { 786 pins = "gpio40"; 787 function = "wcss_wlan2"; 788 drive-strength = <6>; 789 bias-pull-up; 790 }; 791 792 wcss-wlan1-pins { 793 pins = "gpio41"; 794 function = "wcss_wlan1"; 795 drive-strength = <6>; 796 bias-pull-up; 797 }; 798 799 wcss-wlan0-pins { 800 pins = "gpio42"; 801 function = "wcss_wlan0"; 802 drive-strength = <6>; 803 bias-pull-up; 804 }; 805 806 wcss-wlan-pins { 807 pins = "gpio43", "gpio44"; 808 function = "wcss_wlan"; 809 drive-strength = <6>; 810 bias-pull-up; 811 }; 812 }; 813 }; 814 815 gcc: clock-controller@1800000 { 816 compatible = "qcom,gcc-msm8976"; 817 reg = <0x01800000 0x80000>; 818 #clock-cells = <1>; 819 #reset-cells = <1>; 820 #power-domain-cells = <1>; 821 822 assigned-clocks = <&gcc GPLL3>; 823 assigned-clock-rates = <1100000000>; 824 825 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, 826 <&rpmcc RPM_SMD_XO_A_CLK_SRC>, 827 <&mdss_dsi0_phy 1>, 828 <&mdss_dsi0_phy 0>, 829 <&mdss_dsi1_phy 1>, 830 <&mdss_dsi1_phy 0>; 831 clock-names = "xo", 832 "xo_a", 833 "dsi0pll", 834 "dsi0pllbyte", 835 "dsi1pll", 836 "dsi1pllbyte"; 837 }; 838 839 tcsr_mutex: hwlock@1905000 { 840 compatible = "qcom,tcsr-mutex"; 841 reg = <0x01905000 0x20000>; 842 #hwlock-cells = <1>; 843 }; 844 845 tcsr: syscon@1937000 { 846 compatible = "qcom,msm8976-tcsr", "syscon"; 847 reg = <0x01937000 0x30000>; 848 }; 849 850 mdss: display-subsystem@1a00000 { 851 compatible = "qcom,mdss"; 852 853 reg = <0x01a00000 0x1000>, 854 <0x01ab0000 0x3000>; 855 reg-names = "mdss_phys", "vbif_phys"; 856 857 power-domains = <&gcc MDSS_GDSC>; 858 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 859 860 interrupt-controller; 861 #interrupt-cells = <1>; 862 863 clocks = <&gcc GCC_MDSS_AHB_CLK>, 864 <&gcc GCC_MDSS_AXI_CLK>, 865 <&gcc GCC_MDSS_VSYNC_CLK>, 866 <&gcc GCC_MDSS_MDP_CLK>; 867 clock-names = "iface", 868 "bus", 869 "vsync", 870 "core"; 871 872 #address-cells = <1>; 873 #size-cells = <1>; 874 ranges; 875 876 status = "disabled"; 877 878 mdss_mdp: display-controller@1a01000 { 879 compatible = "qcom,msm8976-mdp5", "qcom,mdp5"; 880 reg = <0x01a01000 0x89000>; 881 reg-names = "mdp_phys"; 882 883 interrupt-parent = <&mdss>; 884 interrupts = <0>; 885 886 clocks = <&gcc GCC_MDSS_AHB_CLK>, 887 <&gcc GCC_MDSS_AXI_CLK>, 888 <&gcc GCC_MDSS_MDP_CLK>, 889 <&gcc GCC_MDSS_VSYNC_CLK>, 890 <&gcc GCC_MDP_TBU_CLK>, 891 <&gcc GCC_MDP_RT_TBU_CLK>; 892 clock-names = "iface", 893 "bus", 894 "core", 895 "vsync", 896 "tbu", 897 "tbu_rt"; 898 899 operating-points-v2 = <&mdp_opp_table>; 900 power-domains = <&gcc MDSS_GDSC>; 901 902 iommus = <&apps_iommu 22>; 903 904 ports { 905 #address-cells = <1>; 906 #size-cells = <0>; 907 908 port@0 { 909 reg = <0>; 910 911 mdss_mdp5_intf1_out: endpoint { 912 remote-endpoint = <&mdss_dsi0_in>; 913 }; 914 }; 915 916 port@1 { 917 reg = <1>; 918 919 mdss_mdp5_intf2_out: endpoint { 920 remote-endpoint = <&mdss_dsi1_in>; 921 }; 922 }; 923 }; 924 925 mdp_opp_table: opp-table { 926 compatible = "operating-points-v2"; 927 928 opp-177780000 { 929 opp-hz = /bits/ 64 <177780000>; 930 required-opps = <&rpmpd_opp_svs>; 931 }; 932 933 opp-270000000 { 934 opp-hz = /bits/ 64 <270000000>; 935 required-opps = <&rpmpd_opp_svs_plus>; 936 }; 937 938 opp-320000000 { 939 opp-hz = /bits/ 64 <320000000>; 940 required-opps = <&rpmpd_opp_nom>; 941 }; 942 943 opp-360000000 { 944 opp-hz = /bits/ 64 <360000000>; 945 required-opps = <&rpmpd_opp_turbo>; 946 }; 947 }; 948 }; 949 950 mdss_dsi0: dsi@1a94000 { 951 compatible = "qcom,msm8976-dsi-ctrl", "qcom,mdss-dsi-ctrl"; 952 reg = <0x01a94000 0x300>; 953 reg-names = "dsi_ctrl"; 954 955 interrupt-parent = <&mdss>; 956 interrupts = <4>; 957 958 clocks = <&gcc GCC_MDSS_MDP_CLK>, 959 <&gcc GCC_MDSS_AHB_CLK>, 960 <&gcc GCC_MDSS_AXI_CLK>, 961 <&gcc GCC_MDSS_BYTE0_CLK>, 962 <&gcc GCC_MDSS_PCLK0_CLK>, 963 <&gcc GCC_MDSS_ESC0_CLK>; 964 clock-names = "mdp_core", 965 "iface", 966 "bus", 967 "byte", 968 "pixel", 969 "core"; 970 971 assigned-clocks = <&gcc GCC_MDSS_BYTE0_CLK_SRC>, 972 <&gcc GCC_MDSS_PCLK0_CLK_SRC>; 973 assigned-clock-parents = <&mdss_dsi0_phy 0>, 974 <&mdss_dsi0_phy 1>; 975 976 phys = <&mdss_dsi0_phy>; 977 978 operating-points-v2 = <&dsi0_opp_table>; 979 power-domains = <&gcc MDSS_GDSC>; 980 981 #address-cells = <1>; 982 #size-cells = <0>; 983 984 status = "disabled"; 985 986 ports { 987 #address-cells = <1>; 988 #size-cells = <0>; 989 990 port@0 { 991 reg = <0>; 992 993 mdss_dsi0_in: endpoint { 994 remote-endpoint = <&mdss_mdp5_intf1_out>; 995 }; 996 }; 997 998 port@1 { 999 reg = <1>; 1000 1001 mdss_dsi0_out: endpoint { 1002 }; 1003 }; 1004 }; 1005 1006 dsi0_opp_table: opp-table { 1007 compatible = "operating-points-v2"; 1008 1009 opp-125000000 { 1010 opp-hz = /bits/ 64 <125000000>; 1011 required-opps = <&rpmpd_opp_svs>; 1012 }; 1013 1014 opp-161250000 { 1015 opp-hz = /bits/ 64 <161250000>; 1016 required-opps = <&rpmpd_opp_svs_plus>; 1017 }; 1018 1019 opp-187500000 { 1020 opp-hz = /bits/ 64 <187500000>; 1021 required-opps = <&rpmpd_opp_nom>; 1022 }; 1023 }; 1024 }; 1025 1026 mdss_dsi1: dsi@1a96000 { 1027 compatible = "qcom,msm8976-dsi-ctrl", "qcom,mdss-dsi-ctrl"; 1028 reg = <0x01a96000 0x300>; 1029 reg-names = "dsi_ctrl"; 1030 1031 interrupt-parent = <&mdss>; 1032 interrupts = <5>; 1033 1034 clocks = <&gcc GCC_MDSS_MDP_CLK>, 1035 <&gcc GCC_MDSS_AHB_CLK>, 1036 <&gcc GCC_MDSS_AXI_CLK>, 1037 <&gcc GCC_MDSS_BYTE1_CLK>, 1038 <&gcc GCC_MDSS_PCLK1_CLK>, 1039 <&gcc GCC_MDSS_ESC1_CLK>; 1040 clock-names = "mdp_core", 1041 "iface", 1042 "bus", 1043 "byte", 1044 "pixel", 1045 "core"; 1046 1047 assigned-clocks = <&gcc GCC_MDSS_BYTE1_CLK_SRC>, 1048 <&gcc GCC_MDSS_PCLK1_CLK_SRC>; 1049 assigned-clock-parents = <&mdss_dsi1_phy 0>, 1050 <&mdss_dsi1_phy 1>; 1051 1052 phys = <&mdss_dsi1_phy>; 1053 1054 operating-points-v2 = <&dsi0_opp_table>; 1055 power-domains = <&gcc MDSS_GDSC>; 1056 1057 #address-cells = <1>; 1058 #size-cells = <0>; 1059 1060 status = "disabled"; 1061 1062 ports { 1063 #address-cells = <1>; 1064 #size-cells = <0>; 1065 1066 port@0 { 1067 reg = <0>; 1068 1069 mdss_dsi1_in: endpoint { 1070 remote-endpoint = <&mdss_mdp5_intf2_out>; 1071 }; 1072 }; 1073 1074 port@1 { 1075 reg = <1>; 1076 1077 mdss_dsi1_out: endpoint { 1078 }; 1079 }; 1080 }; 1081 }; 1082 1083 mdss_dsi0_phy: phy@1a94a00 { 1084 compatible = "qcom,dsi-phy-28nm-hpm-fam-b"; 1085 reg = <0x01a94a00 0xd4>, 1086 <0x01a94400 0x280>, 1087 <0x01a94b80 0x30>; 1088 reg-names = "dsi_pll", 1089 "dsi_phy", 1090 "dsi_phy_regulator"; 1091 1092 #clock-cells = <1>; 1093 #phy-cells = <0>; 1094 1095 clocks = <&gcc GCC_MDSS_AHB_CLK>, 1096 <&rpmcc RPM_SMD_XO_CLK_SRC>; 1097 clock-names = "iface", "ref"; 1098 1099 status = "disabled"; 1100 }; 1101 1102 mdss_dsi1_phy: phy@1a96a00 { 1103 compatible = "qcom,dsi-phy-28nm-hpm-fam-b"; 1104 reg = <0x01a96a00 0xd4>, 1105 <0x01a96400 0x280>, 1106 <0x01a96b80 0x30>; 1107 reg-names = "dsi_pll", 1108 "dsi_phy", 1109 "dsi_phy_regulator"; 1110 1111 #clock-cells = <1>; 1112 #phy-cells = <0>; 1113 1114 clocks = <&gcc GCC_MDSS_AHB_CLK>, 1115 <&rpmcc RPM_SMD_XO_CLK_SRC>; 1116 clock-names = "iface", "ref"; 1117 1118 status = "disabled"; 1119 }; 1120 }; 1121 1122 adreno_gpu: gpu@1c00000 { 1123 compatible = "qcom,adreno-510.0", "qcom,adreno"; 1124 1125 reg = <0x01c00000 0x40000>; 1126 reg-names = "kgsl_3d0_reg_memory"; 1127 1128 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 1129 interrupt-names = "kgsl_3d0_irq"; 1130 1131 clocks = <&gcc GCC_GFX3D_OXILI_CLK>, 1132 <&gcc GCC_GFX3D_OXILI_AHB_CLK>, 1133 <&gcc GCC_GFX3D_OXILI_GMEM_CLK>, 1134 <&gcc GCC_GFX3D_BIMC_CLK>, 1135 <&gcc GCC_GFX3D_OXILI_TIMER_CLK>, 1136 <&gcc GCC_GFX3D_OXILI_AON_CLK>; 1137 clock-names = "core", 1138 "iface", 1139 "mem", 1140 "mem_iface", 1141 "rbbmtimer", 1142 "alwayson"; 1143 1144 power-domains = <&gcc OXILI_GX_GDSC>; 1145 1146 iommus = <&gpu_iommu 0>; 1147 1148 operating-points-v2 = <&gpu_opp_table>; 1149 1150 status = "disabled"; 1151 1152 gpu_opp_table: opp-table { 1153 compatible = "operating-points-v2"; 1154 1155 opp-200000000 { 1156 opp-hz = /bits/ 64 <200000000>; 1157 required-opps = <&rpmpd_opp_low_svs>; 1158 opp-supported-hw = <0xff>; 1159 }; 1160 1161 opp-300000000 { 1162 opp-hz = /bits/ 64 <300000000>; 1163 required-opps = <&rpmpd_opp_svs>; 1164 opp-supported-hw = <0xff>; 1165 }; 1166 1167 opp-400000000 { 1168 opp-hz = /bits/ 64 <400000000>; 1169 required-opps = <&rpmpd_opp_nom>; 1170 opp-supported-hw = <0xff>; 1171 }; 1172 1173 opp-480000000 { 1174 opp-hz = /bits/ 64 <480000000>; 1175 required-opps = <&rpmpd_opp_nom_plus>; 1176 opp-supported-hw = <0xff>; 1177 }; 1178 1179 opp-540000000 { 1180 opp-hz = /bits/ 64 <540000000>; 1181 required-opps = <&rpmpd_opp_turbo>; 1182 opp-supported-hw = <0xff>; 1183 }; 1184 1185 opp-600000000 { 1186 opp-hz = /bits/ 64 <600000000>; 1187 required-opps = <&rpmpd_opp_turbo>; 1188 opp-supported-hw = <0xff>; 1189 }; 1190 }; 1191 }; 1192 1193 apps_iommu: iommu@1ee0000 { 1194 compatible = "qcom,msm8976-iommu", "qcom,msm-iommu-v2"; 1195 reg = <0x01ee0000 0x3000>; 1196 ranges = <0 0x01e20000 0x20000>; 1197 1198 clocks = <&gcc GCC_SMMU_CFG_CLK>, 1199 <&gcc GCC_APSS_TCU_CLK>; 1200 clock-names = "iface", "bus"; 1201 1202 qcom,iommu-secure-id = <17>; 1203 1204 #address-cells = <1>; 1205 #size-cells = <1>; 1206 #iommu-cells = <1>; 1207 1208 /* VFE */ 1209 iommu-ctx@15000 { 1210 compatible = "qcom,msm-iommu-v2-ns"; 1211 reg = <0x15000 0x1000>; 1212 qcom,ctx-asid = <20>; 1213 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 1214 }; 1215 1216 /* VENUS NS */ 1217 iommu-ctx@16000 { 1218 compatible = "qcom,msm-iommu-v2-ns"; 1219 reg = <0x16000 0x1000>; 1220 qcom,ctx-asid = <21>; 1221 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 1222 }; 1223 1224 /* MDP0 */ 1225 iommu-ctx@17000 { 1226 compatible = "qcom,msm-iommu-v2-ns"; 1227 reg = <0x17000 0x1000>; 1228 qcom,ctx-asid = <22>; 1229 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 1230 }; 1231 }; 1232 1233 gpu_iommu: iommu@1f08000 { 1234 compatible = "qcom,msm8976-iommu", "qcom,msm-iommu-v2"; 1235 ranges = <0 0x01f08000 0x8000>; 1236 1237 clocks = <&gcc GCC_SMMU_CFG_CLK>, 1238 <&gcc GCC_GFX3D_TCU_CLK>; 1239 clock-names = "iface", "bus"; 1240 1241 power-domains = <&gcc OXILI_CX_GDSC>; 1242 1243 qcom,iommu-secure-id = <18>; 1244 1245 #address-cells = <1>; 1246 #size-cells = <1>; 1247 #iommu-cells = <1>; 1248 1249 /* gfx3d user */ 1250 iommu-ctx@0 { 1251 compatible = "qcom,msm-iommu-v2-ns"; 1252 reg = <0x0 0x1000>; 1253 qcom,ctx-asid = <0>; 1254 interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>; 1255 }; 1256 1257 /* gfx3d secure */ 1258 iommu-ctx@1000 { 1259 compatible = "qcom,msm-iommu-v2-sec"; 1260 reg = <0x1000 0x1000>; 1261 qcom,ctx-asid = <2>; 1262 interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>; 1263 }; 1264 1265 /* gfx3d priv */ 1266 iommu-ctx@2000 { 1267 compatible = "qcom,msm-iommu-v2-sec"; 1268 reg = <0x2000 0x1000>; 1269 qcom,ctx-asid = <1>; 1270 interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>; 1271 }; 1272 }; 1273 1274 spmi_bus: spmi@200f000 { 1275 compatible = "qcom,spmi-pmic-arb"; 1276 reg = <0x0200f000 0x1000>, 1277 <0x02400000 0x800000>, 1278 <0x02c00000 0x800000>, 1279 <0x03800000 0x200000>, 1280 <0x0200a000 0x2100>; 1281 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 1282 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; 1283 interrupt-names = "periph_irq"; 1284 qcom,channel = <0>; 1285 qcom,ee = <0>; 1286 1287 #address-cells = <2>; 1288 #size-cells = <0>; 1289 interrupt-controller; 1290 #interrupt-cells = <4>; 1291 }; 1292 1293 sdhc_1: mmc@7824900 { 1294 compatible = "qcom,msm8976-sdhci", "qcom,sdhci-msm-v4"; 1295 reg = <0x07824900 0x500>, <0x07824000 0x800>; 1296 reg-names = "hc", "core"; 1297 1298 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 1299 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 1300 interrupt-names = "hc_irq", "pwr_irq"; 1301 1302 clocks = <&gcc GCC_SDCC1_AHB_CLK>, 1303 <&gcc GCC_SDCC1_APPS_CLK>, 1304 <&rpmcc RPM_SMD_XO_CLK_SRC>; 1305 clock-names = "iface", "core", "xo"; 1306 status = "disabled"; 1307 }; 1308 1309 sdhc_2: mmc@7864900 { 1310 compatible = "qcom,msm8976-sdhci", "qcom,sdhci-msm-v4"; 1311 reg = <0x07864900 0x11c>, <0x07864000 0x800>; 1312 reg-names = "hc", "core"; 1313 1314 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 1315 <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; 1316 interrupt-names = "hc_irq", "pwr_irq"; 1317 1318 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 1319 <&gcc GCC_SDCC2_APPS_CLK>, 1320 <&rpmcc RPM_SMD_XO_CLK_SRC>; 1321 clock-names = "iface", "core", "xo"; 1322 status = "disabled"; 1323 }; 1324 1325 blsp1_dma: dma-controller@7884000 { 1326 compatible = "qcom,bam-v1.7.0"; 1327 reg = <0x07884000 0x1f000>; 1328 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>; 1329 clocks = <&gcc GCC_BLSP1_AHB_CLK>; 1330 clock-names = "bam_clk"; 1331 #dma-cells = <1>; 1332 qcom,ee = <0>; 1333 }; 1334 1335 blsp1_uart1: serial@78af000 { 1336 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 1337 reg = <0x078af000 0x200>; 1338 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 1339 clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; 1340 clock-names = "core", "iface"; 1341 dmas = <&blsp1_dma 0>, <&blsp1_dma 1>; 1342 dma-names = "tx", "rx"; 1343 status = "disabled"; 1344 }; 1345 1346 blsp1_uart2: serial@78b0000 { 1347 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 1348 reg = <0x078b0000 0x200>; 1349 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 1350 clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; 1351 clock-names = "core", "iface"; 1352 dmas = <&blsp1_dma 2>, <&blsp1_dma 3>; 1353 dma-names = "tx", "rx"; 1354 status = "disabled"; 1355 }; 1356 1357 blsp1_spi1: spi@78b5000 { 1358 compatible = "qcom,spi-qup-v2.2.1"; 1359 reg = <0x078b5000 0x500>; 1360 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 1361 clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; 1362 clock-names = "core", "iface"; 1363 dmas = <&blsp1_dma 4>, <&blsp1_dma 5>; 1364 dma-names = "tx", "rx"; 1365 pinctrl-names = "default", "sleep"; 1366 pinctrl-0 = <&spi1_default>; 1367 pinctrl-1 = <&spi1_sleep>; 1368 #address-cells = <1>; 1369 #size-cells = <0>; 1370 status = "disabled"; 1371 }; 1372 1373 blsp1_i2c2: i2c@78b6000 { 1374 compatible = "qcom,i2c-qup-v2.2.1"; 1375 reg = <0x078b6000 0x500>; 1376 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 1377 clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; 1378 clock-names = "core", "iface"; 1379 clock-frequency = <400000>; 1380 dmas = <&blsp1_dma 6>, <&blsp1_dma 7>; 1381 dma-names = "tx", "rx"; 1382 pinctrl-names = "default", "sleep"; 1383 pinctrl-0 = <&blsp1_i2c2_default>; 1384 pinctrl-1 = <&blsp1_i2c2_default>; 1385 #address-cells = <1>; 1386 #size-cells = <0>; 1387 status = "disabled"; 1388 }; 1389 1390 blsp1_i2c4: i2c@78b8000 { 1391 compatible = "qcom,i2c-qup-v2.2.1"; 1392 reg = <0x078b8000 0x500>; 1393 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 1394 clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; 1395 clock-names = "core", "iface"; 1396 clock-frequency = <400000>; 1397 dmas = <&blsp1_dma 10>, <&blsp1_dma 11>; 1398 dma-names = "tx", "rx"; 1399 pinctrl-names = "default", "sleep"; 1400 pinctrl-0 = <&blsp1_i2c4_default>; 1401 pinctrl-1 = <&blsp1_i2c4_sleep>; 1402 #address-cells = <1>; 1403 #size-cells = <0>; 1404 status = "disabled"; 1405 }; 1406 1407 otg: usb@78db000 { 1408 compatible = "qcom,ci-hdrc"; 1409 reg = <0x078db000 0x200>, 1410 <0x078db200 0x200>; 1411 interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, 1412 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 1413 clocks = <&gcc GCC_USB_HS_AHB_CLK>, <&gcc GCC_USB_HS_SYSTEM_CLK>; 1414 clock-names = "iface", "core"; 1415 assigned-clocks = <&gcc GCC_USB_HS_SYSTEM_CLK>; 1416 assigned-clock-rates = <80000000>; 1417 resets = <&gcc RST_USB_HS_BCR>; 1418 reset-names = "core"; 1419 ahb-burst-config = <0>; 1420 dr_mode = "peripheral"; 1421 phy_type = "ulpi"; 1422 phy-names = "usb-phy"; 1423 phys = <&usb_hs_phy>; 1424 status = "disabled"; 1425 #reset-cells = <1>; 1426 }; 1427 1428 sdhc_3: mmc@7a24900 { 1429 compatible = "qcom,msm8976-sdhci", "qcom,sdhci-msm-v4"; 1430 reg = <0x07a24900 0x11c>, <0x07a24000 0x800>; 1431 reg-names = "hc", "core"; 1432 1433 interrupts = <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, 1434 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>; 1435 interrupt-names = "hc_irq", "pwr_irq"; 1436 1437 clocks = <&gcc GCC_SDCC3_AHB_CLK>, 1438 <&gcc GCC_SDCC3_APPS_CLK>, 1439 <&rpmcc RPM_SMD_XO_CLK_SRC>; 1440 clock-names = "iface", "core", "xo"; 1441 1442 status = "disabled"; 1443 }; 1444 1445 blsp2_dma: dma-controller@7ac4000 { 1446 compatible = "qcom,bam-v1.7.0"; 1447 reg = <0x07ac4000 0x1f000>; 1448 interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>; 1449 clocks = <&gcc GCC_BLSP2_AHB_CLK>; 1450 clock-names = "bam_clk"; 1451 #dma-cells = <1>; 1452 qcom,ee = <0>; 1453 }; 1454 1455 blsp2_uart2: serial@7af0000 { 1456 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 1457 reg = <0x07af0000 0x200>; 1458 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>; 1459 clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>; 1460 clock-names = "core", "iface"; 1461 dmas = <&blsp2_dma 0>, <&blsp2_dma 1>; 1462 dma-names = "tx", "rx"; 1463 status = "disabled"; 1464 }; 1465 1466 blsp2_i2c2: i2c@7af6000 { 1467 compatible = "qcom,i2c-qup-v2.2.1"; 1468 reg = <0x07af6000 0x600>; 1469 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 1470 clocks = <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>; 1471 clock-names = "core", "iface"; 1472 clock-frequency = <400000>; 1473 dmas = <&blsp2_dma 6>, <&blsp2_dma 7>; 1474 dma-names = "tx", "rx"; 1475 pinctrl-names = "default", "sleep"; 1476 pinctrl-0 = <&blsp2_i2c2_default>; 1477 pinctrl-1 = <&blsp2_i2c2_sleep>; 1478 #address-cells = <1>; 1479 #size-cells = <0>; 1480 status = "disabled"; 1481 }; 1482 1483 blsp2_i2c4: i2c@7af8000 { 1484 compatible = "qcom,i2c-qup-v2.2.1"; 1485 reg = <0x07af8000 0x600>; 1486 interrupts = <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>; 1487 clocks = <&gcc GCC_BLSP2_QUP4_I2C_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>; 1488 clock-names = "core", "iface"; 1489 clock-frequency = <400000>; 1490 dmas = <&blsp2_dma 10>, <&blsp2_dma 11>; 1491 dma-names = "tx", "rx"; 1492 pinctrl-names = "default", "sleep"; 1493 pinctrl-0 = <&blsp2_i2c4_default>; 1494 pinctrl-1 = <&blsp2_i2c4_sleep>; 1495 #address-cells = <1>; 1496 #size-cells = <0>; 1497 status = "disabled"; 1498 }; 1499 1500 wcnss: remoteproc@a204000 { 1501 compatible = "qcom,pronto-v3-pil", "qcom,pronto"; 1502 reg = <0x0a204000 0x2000>, 1503 <0x0a202000 0x1000>, 1504 <0x0a21b000 0x3000>; 1505 reg-names = "ccu", 1506 "dxe", 1507 "pmu"; 1508 1509 memory-region = <&wcnss_fw_mem>; 1510 1511 interrupts-extended = <&intc GIC_SPI 149 IRQ_TYPE_EDGE_RISING>, 1512 <&wcnss_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 1513 <&wcnss_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 1514 <&wcnss_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 1515 <&wcnss_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 1516 interrupt-names = "wdog", 1517 "fatal", 1518 "ready", 1519 "handover", 1520 "stop-ack"; 1521 1522 power-domains = <&rpmpd MSM8976_VDDCX>, 1523 <&rpmpd MSM8976_VDDMX>; 1524 power-domain-names = "cx", "mx"; 1525 1526 qcom,smem-states = <&wcnss_smp2p_out 0>; 1527 qcom,smem-state-names = "stop"; 1528 1529 pinctrl-0 = <&wcss_wlan_default>; 1530 pinctrl-names = "default"; 1531 1532 status = "disabled"; 1533 1534 wcnss_iris: iris { 1535 /* Separate chip, compatible is board-specific */ 1536 clocks = <&rpmcc RPM_SMD_RF_CLK2>; 1537 clock-names = "xo"; 1538 }; 1539 1540 smd-edge { 1541 interrupts = <GIC_SPI 142 IRQ_TYPE_EDGE_RISING>; 1542 1543 mboxes = <&apcs 17>; 1544 qcom,smd-edge = <6>; 1545 qcom,remote-pid = <4>; 1546 1547 label = "pronto"; 1548 1549 wcnss_ctrl: wcnss { 1550 compatible = "qcom,wcnss"; 1551 qcom,smd-channels = "WCNSS_CTRL"; 1552 1553 qcom,mmio = <&wcnss>; 1554 1555 wcnss_bt: bluetooth { 1556 compatible = "qcom,wcnss-bt"; 1557 }; 1558 1559 wcnss_wifi: wifi { 1560 compatible = "qcom,wcnss-wlan"; 1561 1562 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 1563 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; 1564 interrupt-names = "tx", "rx"; 1565 1566 qcom,smem-states = <&apps_smsm 10>, 1567 <&apps_smsm 9>; 1568 qcom,smem-state-names = "tx-enable", 1569 "tx-rings-empty"; 1570 }; 1571 }; 1572 }; 1573 }; 1574 1575 intc: interrupt-controller@b000000 { 1576 compatible = "qcom,msm-qgic2"; 1577 reg = <0x0b000000 0x1000>, <0x0b002000 0x1000>; 1578 interrupt-controller; 1579 #interrupt-cells = <3>; 1580 }; 1581 1582 apcs: mailbox@b011000 { 1583 compatible = "qcom,msm8976-apcs-kpss-global", 1584 "qcom,msm8994-apcs-kpss-global", "syscon"; 1585 reg = <0x0b011000 0x1000>; 1586 #mbox-cells = <1>; 1587 }; 1588 1589 timer@b120000 { 1590 compatible = "arm,armv7-timer-mem"; 1591 reg = <0x0b120000 0x1000>; 1592 #address-cells = <1>; 1593 #size-cells = <1>; 1594 ranges; 1595 clock-frequency = <19200000>; 1596 1597 frame@b121000 { 1598 reg = <0x0b121000 0x1000>, <0x0b122000 0x1000>; 1599 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 1600 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 1601 frame-number = <0>; 1602 }; 1603 1604 frame@b123000 { 1605 reg = <0x0b123000 0x1000>; 1606 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 1607 frame-number = <1>; 1608 status = "disabled"; 1609 }; 1610 1611 frame@b124000 { 1612 reg = <0x0b124000 0x1000>; 1613 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 1614 frame-number = <2>; 1615 status = "disabled"; 1616 }; 1617 1618 frame@b125000 { 1619 reg = <0x0b125000 0x1000>; 1620 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 1621 frame-number = <3>; 1622 status = "disabled"; 1623 }; 1624 1625 frame@b126000 { 1626 reg = <0x0b126000 0x1000>; 1627 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 1628 frame-number = <4>; 1629 status = "disabled"; 1630 }; 1631 1632 frame@b127000 { 1633 reg = <0x0b127000 0x1000>; 1634 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 1635 frame-number = <5>; 1636 status = "disabled"; 1637 }; 1638 1639 frame@b128000 { 1640 reg = <0x0b128000 0x1000>; 1641 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 1642 frame-number = <6>; 1643 status = "disabled"; 1644 }; 1645 }; 1646 1647 imem: sram@8600000 { 1648 compatible = "qcom,msm8976-imem", "syscon", "simple-mfd"; 1649 reg = <0x08600000 0x1000>; 1650 #address-cells = <1>; 1651 #size-cells = <1>; 1652 1653 ranges = <0 0x08600000 0x1000>; 1654 1655 pil-reloc@94c { 1656 compatible = "qcom,pil-reloc-info"; 1657 reg = <0x94c 0xc8>; 1658 }; 1659 }; 1660 }; 1661 1662 thermal-zones { 1663 aoss0-thermal { 1664 polling-delay-passive = <250>; 1665 1666 thermal-sensors = <&tsens 0>; 1667 1668 trips { 1669 aoss0_alert0: trip-point0 { 1670 temperature = <75000>; 1671 hysteresis = <2000>; 1672 type = "hot"; 1673 }; 1674 }; 1675 }; 1676 1677 modem-thermal { 1678 polling-delay-passive = <250>; 1679 1680 thermal-sensors = <&tsens 1>; 1681 trips { 1682 modem_alert0: trip-point0 { 1683 temperature = <75000>; 1684 hysteresis = <2000>; 1685 type = "hot"; 1686 }; 1687 }; 1688 }; 1689 1690 qdsp-thermal { 1691 polling-delay-passive = <250>; 1692 1693 thermal-sensors = <&tsens 2>; 1694 trips { 1695 qdsp_alert0: trip-point0 { 1696 temperature = <75000>; 1697 hysteresis = <2000>; 1698 type = "hot"; 1699 }; 1700 }; 1701 }; 1702 1703 cam-isp-thermal { 1704 polling-delay-passive = <250>; 1705 1706 thermal-sensors = <&tsens 3>; 1707 trips { 1708 cam_isp_alert0: trip-point0 { 1709 temperature = <75000>; 1710 hysteresis = <2000>; 1711 type = "hot"; 1712 }; 1713 }; 1714 }; 1715 1716 cpu4-thermal { 1717 polling-delay-passive = <250>; 1718 1719 thermal-sensors = <&tsens 4>; 1720 1721 trips { 1722 cpu4_alert0: trip-point0 { 1723 temperature = <50000>; 1724 hysteresis = <2000>; 1725 type = "hot"; 1726 }; 1727 cpu4_alert1: trip-point1 { 1728 temperature = <55000>; 1729 hysteresis = <2000>; 1730 type = "passive"; 1731 }; 1732 cpu4_crit: cpu-crit { 1733 temperature = <75000>; 1734 hysteresis = <2000>; 1735 type = "critical"; 1736 }; 1737 }; 1738 }; 1739 1740 cpu5-thermal { 1741 polling-delay-passive = <250>; 1742 1743 thermal-sensors = <&tsens 5>; 1744 1745 trips { 1746 cpu5_alert0: trip-point0 { 1747 temperature = <50000>; 1748 hysteresis = <2000>; 1749 type = "hot"; 1750 }; 1751 cpu5_alert1: trip-point1 { 1752 temperature = <55000>; 1753 hysteresis = <2000>; 1754 type = "passive"; 1755 }; 1756 cpu5_crit: cpu-crit { 1757 temperature = <75000>; 1758 hysteresis = <2000>; 1759 type = "critical"; 1760 }; 1761 }; 1762 }; 1763 1764 cpu6-thermal { 1765 polling-delay-passive = <250>; 1766 1767 thermal-sensors = <&tsens 6>; 1768 1769 trips { 1770 cpu6_alert0: trip-point0 { 1771 temperature = <50000>; 1772 hysteresis = <2000>; 1773 type = "hot"; 1774 }; 1775 cpu6_alert1: trip-point1 { 1776 temperature = <55000>; 1777 hysteresis = <2000>; 1778 type = "passive"; 1779 }; 1780 cpu6_crit: cpu-crit { 1781 temperature = <75000>; 1782 hysteresis = <2000>; 1783 type = "critical"; 1784 }; 1785 }; 1786 }; 1787 1788 cpu7-thermal { 1789 polling-delay-passive = <250>; 1790 1791 thermal-sensors = <&tsens 7>; 1792 1793 trips { 1794 cpu7_alert0: trip-point0 { 1795 temperature = <50000>; 1796 hysteresis = <2000>; 1797 type = "hot"; 1798 }; 1799 cpu7_alert1: trip-point1 { 1800 temperature = <55000>; 1801 hysteresis = <2000>; 1802 type = "passive"; 1803 }; 1804 cpu7_crit: cpu-crit { 1805 temperature = <75000>; 1806 hysteresis = <2000>; 1807 type = "critical"; 1808 }; 1809 }; 1810 }; 1811 1812 big-l2-thermal { 1813 polling-delay-passive = <250>; 1814 1815 thermal-sensors = <&tsens 8>; 1816 1817 trips { 1818 l2_alert0: trip-point0 { 1819 temperature = <50000>; 1820 hysteresis = <2000>; 1821 type = "hot"; 1822 }; 1823 l2_alert1: trip-point1 { 1824 temperature = <55000>; 1825 hysteresis = <2000>; 1826 type = "passive"; 1827 }; 1828 l2_crit: l2-crit { 1829 temperature = <75000>; 1830 hysteresis = <2000>; 1831 type = "critical"; 1832 }; 1833 }; 1834 }; 1835 1836 cpu0-thermal { 1837 polling-delay-passive = <250>; 1838 1839 thermal-sensors = <&tsens 9>; 1840 1841 trips { 1842 cpu0_alert0: trip-point0 { 1843 temperature = <50000>; 1844 hysteresis = <2000>; 1845 type = "hot"; 1846 }; 1847 cpu0_alert1: trip-point1 { 1848 temperature = <55000>; 1849 hysteresis = <2000>; 1850 type = "passive"; 1851 }; 1852 cpu0_crit: cpu-crit { 1853 temperature = <75000>; 1854 hysteresis = <2000>; 1855 type = "critical"; 1856 }; 1857 }; 1858 }; 1859 1860 gpu-thermal { 1861 polling-delay-passive = <250>; 1862 1863 thermal-sensors = <&tsens 10>; 1864 1865 trips { 1866 gpu_alert0: trip-point0 { 1867 temperature = <50000>; 1868 hysteresis = <2000>; 1869 type = "hot"; 1870 }; 1871 gpu_alert1: trip-point1 { 1872 temperature = <55000>; 1873 hysteresis = <2000>; 1874 type = "passive"; 1875 }; 1876 gpu_crit: gpu-crit { 1877 temperature = <75000>; 1878 hysteresis = <2000>; 1879 type = "critical"; 1880 }; 1881 }; 1882 }; 1883 }; 1884 1885 timer { 1886 compatible = "arm,armv8-timer"; 1887 interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 1888 <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 1889 <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 1890 <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; 1891 clock-frequency = <19200000>; 1892 }; 1893}; 1894