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/linux-6.12.1/Documentation/devicetree/bindings/media/
Drenesas,fdp1.yaml62 reg = <0xfe940000 0x2400>;
/linux-6.12.1/Documentation/devicetree/bindings/display/
Drenesas,shmobile-lcdc.yaml49 port@0:
65 - port@0
111 reg = <0xfe940000 0x4000>;
121 #size-cells = <0>;
123 port@0 {
124 reg = <0>;
/linux-6.12.1/arch/sh/boards/mach-ap325rxa/
Dsetup.c60 [0] = {
61 .start = 0xb6080000,
62 .end = 0xb60fffff,
66 .start = evt2irq(0x660),
67 .end = evt2irq(0x660),
83 * AP320 and AP325RXA has CPLD data in NOR Flash(0xA80000-0xABFFFF).
89 .offset = 0,
119 [0] = {
121 .start = 0x00000000,
122 .end = 0x00ffffff,
[all …]
/linux-6.12.1/arch/sh/boards/mach-kfr2r09/
Dsetup.c49 #define DRVCRB 0xA405018C
55 .offset = 0,
73 [0] = {
75 .start = 0x00000000,
76 .end = 0x03ffffff,
91 [0] = {
93 .start = 0x10000000,
94 .end = 0x1001ffff,
111 KEY_1, KEY_2, KEY_3, 0, KEY_UP,
112 KEY_4, KEY_5, KEY_6, 0, KEY_LEFT,
[all …]
/linux-6.12.1/arch/sh/boards/mach-migor/
Dsetup.c41 * 0x00000000 64MB 16 NOR Flash (SP29PL256N)
42 * 0x0c000000 64MB 64 SDRAM (2xK4M563233G)
43 * 0x10000000 IRQ0 16 Ethernet (SMC91C111)
44 * 0x14000000 IRQ4 16 USB 2.0 Host Controller (M66596)
45 * 0x18000000 8GB 8 NAND Flash (K9K8G08U0A)
56 [0] = {
58 .start = 0x10000300,
59 .end = 0x1000030f,
63 .start = evt2irq(0x600), /* IRQ0 */
82 0, KEY_UP, KEY_DOWN, KEY_LEFT, KEY_RIGHT, KEY_ENTER,
[all …]
/linux-6.12.1/arch/arm/boot/dts/renesas/
Dr8a7740.dtsi20 #size-cells = <0>;
21 cpu@0 {
24 reg = <0x0>;
35 reg = <0xc2800000 0x1000>,
36 <0xc2000000 0x1000>;
41 reg = <0xf0100000 0x1000>;
53 reg = <0xfe400000 0x400>;
68 reg = <0xfe910000 0x3000>;
77 reg = <0xfe914000 0x3000>;
87 reg = <0xe6138000 0x170>;
[all …]
Dr8a7794.dtsi34 * The external audio clocks are configured as 0 Hz fixed frequency
40 #clock-cells = <0>;
41 clock-frequency = <0>;
45 #clock-cells = <0>;
46 clock-frequency = <0>;
50 #clock-cells = <0>;
51 clock-frequency = <0>;
57 #clock-cells = <0>;
59 clock-frequency = <0>;
64 #size-cells = <0>;
[all …]
Dr8a7793.dtsi32 * The external audio clocks are configured as 0 Hz fixed frequency
38 #clock-cells = <0>;
39 clock-frequency = <0>;
43 #clock-cells = <0>;
44 clock-frequency = <0>;
48 #clock-cells = <0>;
49 clock-frequency = <0>;
55 #clock-cells = <0>;
57 clock-frequency = <0>;
62 #size-cells = <0>;
[all …]
Dr8a7790.dtsi41 * The external audio clocks are configured as 0 Hz fixed frequency
47 #clock-cells = <0>;
48 clock-frequency = <0>;
52 #clock-cells = <0>;
53 clock-frequency = <0>;
57 #clock-cells = <0>;
58 clock-frequency = <0>;
64 #clock-cells = <0>;
66 clock-frequency = <0>;
71 #size-cells = <0>;
[all …]
Dr8a7791.dtsi40 * The external audio clocks are configured as 0 Hz fixed frequency
46 #clock-cells = <0>;
47 clock-frequency = <0>;
51 #clock-cells = <0>;
52 clock-frequency = <0>;
56 #clock-cells = <0>;
57 clock-frequency = <0>;
63 #clock-cells = <0>;
65 clock-frequency = <0>;
70 #size-cells = <0>;
[all …]
/linux-6.12.1/arch/sh/boards/mach-se/7724/
Dsetup.c55 * SW41 : abxx xxxx -> a = 0 : Analog monitor
57 * b = 0 : VGA
96 [0] = {
98 .start = 0x1a300300,
99 .end = 0x1a30030f,
121 .offset = 0,
142 [0] = {
144 .start = 0x00000000,
145 .end = 0x01ffffff,
163 .sync = 0, /* hsync and vsync are active low */
[all …]
/linux-6.12.1/arch/sh/kernel/cpu/sh4a/
Dsetup-sh7724.c37 .addr = 0xffe0000c,
39 .mid_rid = 0x21,
42 .addr = 0xffe00014,
44 .mid_rid = 0x22,
47 .addr = 0xffe1000c,
49 .mid_rid = 0x25,
52 .addr = 0xffe10014,
54 .mid_rid = 0x26,
57 .addr = 0xffe2000c,
59 .mid_rid = 0x29,
[all …]
/linux-6.12.1/arch/sh/boards/mach-ecovec24/
Dsetup.c53 * 0x0000_0000 uboot 16bit
54 * 0x0004_0000 Linux romImage 16bit
55 * 0x0014_0000 MTD for Linux 16bit
56 * 0x0400_0000 Internal I/O 16/32bit
57 * 0x0800_0000 DRAM 32bit
58 * 0x1800_0000 MFI 16bit
90 static unsigned char led_pos[] = { 0, 1, 2, 3 };
98 .start = 0xA405012C, /* PTG */
99 .end = 0xA405012E - 1,
117 .offset = 0,
[all …]
/linux-6.12.1/arch/arm64/boot/dts/renesas/
Dr8a774a1.dtsi19 * The external audio clocks are configured as 0 Hz fixed frequency
25 #clock-cells = <0>;
26 clock-frequency = <0>;
31 #clock-cells = <0>;
32 clock-frequency = <0>;
37 #clock-cells = <0>;
38 clock-frequency = <0>;
44 #clock-cells = <0>;
45 clock-frequency = <0>;
48 cluster0_opp: opp-table-0 {
[all …]
Dr8a774b1.dtsi19 * The external audio clocks are configured as 0 Hz fixed frequency
25 #clock-cells = <0>;
26 clock-frequency = <0>;
31 #clock-cells = <0>;
32 clock-frequency = <0>;
37 #clock-cells = <0>;
38 clock-frequency = <0>;
44 #clock-cells = <0>;
45 clock-frequency = <0>;
48 cluster0_opp: opp-table-0 {
[all …]
Dr8a774e1.dtsi19 * The external audio clocks are configured as 0 Hz fixed frequency
25 #clock-cells = <0>;
26 clock-frequency = <0>;
31 #clock-cells = <0>;
32 clock-frequency = <0>;
37 #clock-cells = <0>;
38 clock-frequency = <0>;
44 #clock-cells = <0>;
45 clock-frequency = <0>;
48 cluster0_opp: opp-table-0 {
[all …]
Dr8a77960.dtsi18 * The external audio clocks are configured as 0 Hz fixed frequency
24 #clock-cells = <0>;
25 clock-frequency = <0>;
30 #clock-cells = <0>;
31 clock-frequency = <0>;
36 #clock-cells = <0>;
37 clock-frequency = <0>;
43 #clock-cells = <0>;
44 clock-frequency = <0>;
47 cluster0_opp: opp-table-0 {
[all …]
Dr8a77965.dtsi23 * The external audio clocks are configured as 0 Hz fixed frequency
29 #clock-cells = <0>;
30 clock-frequency = <0>;
35 #clock-cells = <0>;
36 clock-frequency = <0>;
41 #clock-cells = <0>;
42 clock-frequency = <0>;
48 #clock-cells = <0>;
49 clock-frequency = <0>;
52 cluster0_opp: opp-table-0 {
[all …]
Dr8a77951.dtsi23 * The external audio clocks are configured as 0 Hz fixed frequency
29 #clock-cells = <0>;
30 clock-frequency = <0>;
35 #clock-cells = <0>;
36 clock-frequency = <0>;
41 #clock-cells = <0>;
42 clock-frequency = <0>;
48 #clock-cells = <0>;
49 clock-frequency = <0>;
52 cluster0_opp: opp-table-0 {
[all …]