60 	[0] = {
61 		.start	= 0xb6080000,
62 		.end	= 0xb60fffff,
66 		.start	= evt2irq(0x660),
67 		.end	= evt2irq(0x660),
83  * AP320 and AP325RXA has CPLD data in NOR Flash(0xA80000-0xABFFFF).
89 		.offset = 0,
119 	[0] = {
121 		.start	= 0x00000000,
122 		.end	= 0x00ffffff,
139 		.offset	= 0,
145 	[0] = {
146 		.start	= 0xa4530000,
147 		.end	= 0xa45300ff,
168 #define FPGA_LCDREG	0xB4100180
169 #define FPGA_BKLREG	0xB4100212
170 #define FPGA_LCDREG_VAL	0x0018
171 #define PORT_MSELCRB	0xA4050182
172 #define PORT_HIZCRC	0xA405015C
173 #define PORT_DRVCRA	0xA405018A
174 #define PORT_DRVCRB	0xA405018C
179 		gpio_set_value(GPIO_PTS3, 0);  in ap320_wvga_set_brightness()
180 		__raw_writew(0x100, FPGA_BKLREG);  in ap320_wvga_set_brightness()
182 		__raw_writew(0, FPGA_BKLREG);  in ap320_wvga_set_brightness()
186 	return 0;  in ap320_wvga_set_brightness()
200 	__raw_writew(0, FPGA_LCDREG);  in ap320_wvga_power_off()
214 		.sync = 0, /* hsync and vsync are active low */
220 	.ch[0] = {
242 	[0] = {
244 		.start	= 0xfe940000, /* P4-only space */
245 		.end	= 0xfe942fff,
249 		.start	= evt2irq(0x580),
265 	.dev_id		= "0-0021",
274 		{ /* [0] = ov7725  */
275 			.flags		= 0,
277 			.bus_shift	= 0,
278 			.i2c_adapter_id	= 0,
279 			.i2c_address	= 0x21,
285 	[0] = {
287 		.start	= 0xfe910000,
288 		.end	= 0xfe91009f,
292 		.start  = evt2irq(0x880),
299 	.id             = 0, /* "ceu.0" clock */
310 	REGULATOR_SUPPLY("vmmc", "sh_mobile_sdhi.0"),
311 	REGULATOR_SUPPLY("vqmmc", "sh_mobile_sdhi.0"),
317 	[0] = {
319 		.start	= 0x04ce0000,
320 		.end	= 0x04ce00ff,
324 		.start	= evt2irq(0xe80),
335 	.id             = 0, /* "sdhi0" clock */
344 	[0] = {
346 		.start	= 0x04cf0000,
347 		.end	= 0x04cf00ff,
351 		.start	= evt2irq(0x4e0),
372 	.edgectrl	= OV772X_AUTO_EDGECTRL(0xf, 0),
377 		I2C_BOARD_INFO("pcf8563", 0x51),
380 		I2C_BOARD_INFO("ov772x", 0x21),
408 	regulator_register_always_on(0, "fixed-3.3V", fixed3v3_power_consumers,  in ap325rxa_devices_setup()
415 	gpiod_export(gpio_to_desc(GPIO_PTX5), 0);  in ap325rxa_devices_setup()
418 	gpio_direction_output(GPIO_PTX4, 0);  in ap325rxa_devices_setup()
419 	gpiod_export(gpio_to_desc(GPIO_PTX4), 0);  in ap325rxa_devices_setup()
424 	gpiod_export(gpio_to_desc(GPIO_PTF7), 0);  in ap325rxa_devices_setup()
472 	gpio_direction_output(GPIO_PTZ7, 0); /* OE_CAM */  in ap325rxa_devices_setup()
474 	gpio_direction_output(GPIO_PTZ6, 0); /* STBY_CAM */  in ap325rxa_devices_setup()
476 	gpio_direction_output(GPIO_PTZ5, 0); /* RST_CAM */  in ap325rxa_devices_setup()
478 	gpio_direction_output(GPIO_PTZ4, 0); /* SADDR */  in ap325rxa_devices_setup()
480 	__raw_writew(__raw_readw(PORT_MSELCRB) & ~0x0001, PORT_MSELCRB);  in ap325rxa_devices_setup()
498 	__raw_writew(0, PORT_HIZCRC);  in ap325rxa_devices_setup()
499 	__raw_writew(0xFFFF, PORT_DRVCRA);  in ap325rxa_devices_setup()
500 	__raw_writew(0xFFFF, PORT_DRVCRB);  in ap325rxa_devices_setup()
522 	clk_add_alias(NULL, "0-0021", "video_clk", NULL);  in ap325rxa_devices_setup()
527 	i2c_register_board_info(0, ap325rxa_i2c_devices,  in ap325rxa_devices_setup()
546 	/* MD0=0, MD1=0, MD2=0: Clock Mode 0  in ap325rxa_mode_pins()
547 	 * MD3=0: 16-bit Area0 Bus Width  in ap325rxa_mode_pins()