| /linux-6.12.1/drivers/gpu/drm/xe/ |
| D | xe_pm.c | 27 * DOC: Xe Power Management
29 * Xe PM implements the main routines for both system level suspend states and
49 * to perform the transition from D3hot to D3cold. Xe may disallow this
57 * (PC-states), and/or other low level power states. Xe PM component provides
61 * Also, Xe PM provides get and put functions that Xe driver will use to
84 * @xe: The xe device.
89 bool xe_rpm_reclaim_safe(const struct xe_device *xe) in xe_rpm_reclaim_safe() argument
91 return !xe->d3cold.capable && !xe->info.has_sriov; in xe_rpm_reclaim_safe()
94 static void xe_rpm_lockmap_acquire(const struct xe_device *xe) in xe_rpm_lockmap_acquire() argument
96 lock_map_acquire(xe_rpm_reclaim_safe(xe) ? in xe_rpm_lockmap_acquire()
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| D | xe_device.c | 64 struct xe_device *xe = to_xe_device(dev); in xe_file_open() local
82 xef->xe = xe; in xe_file_open()
100 return 0; in xe_file_open()
118 * xe_file_get() - Take a reference to the xe file object
119 * @xef: Pointer to the xe file
121 * Anyone with a pointer to xef must take a reference to the xe file
124 * Return: xe file pointer
133 * xe_file_put() - Drop a reference to the xe file object
134 * @xef: Pointer to the xe file
145 struct xe_device *xe = to_xe_device(dev); in xe_file_close() local
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| D | xe_irq.c | 29 #define IMR(offset) XE_REG(offset + 0x4)
30 #define IIR(offset) XE_REG(offset + 0x8)
31 #define IER(offset) XE_REG(offset + 0xc)
37 if (val == 0) in assert_iir_is_zero()
41 "Interrupt register 0x%x is not zero: 0x%08x\n", in assert_iir_is_zero()
43 xe_mmio_write32(mmio, reg, 0xffffffff); in assert_iir_is_zero()
45 xe_mmio_write32(mmio, reg, 0xffffffff); in assert_iir_is_zero()
75 xe_mmio_write32(mmio, IMR(irqregs), ~0); in mask_and_disable()
79 xe_mmio_write32(mmio, IER(irqregs), 0); in mask_and_disable()
82 xe_mmio_write32(mmio, IIR(irqregs), ~0); in mask_and_disable()
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| D | xe_pat.c | 22 #define _PAT_ATS 0x47fc
24 0x4800, 0x4804, \
25 0x4848, 0x484c)
26 #define _PAT_PTA 0x4820
33 #define XE2_COH_MODE REG_GENMASK(1, 0)
38 #define XELPG_PAT_0_WB REG_FIELD_PREP(XELPG_L4_POLICY_MASK, 0)
39 #define XELPG_INDEX_COH_MODE_MASK REG_GENMASK(1, 0)
42 #define XELPG_0_COH_NON REG_FIELD_PREP(XELPG_INDEX_COH_MODE_MASK, 0)
47 #define XELP_MEM_TYPE_MASK REG_GENMASK(1, 0)
51 #define XELP_PAT_UC REG_FIELD_PREP(XELP_MEM_TYPE_MASK, 0)
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| D | xe_ttm_stolen_mgr.c | 49 * @xe: xe device
55 bool xe_ttm_stolen_cpu_access_needs_ggtt(struct xe_device *xe) in xe_ttm_stolen_cpu_access_needs_ggtt() argument
57 return GRAPHICS_VERx100(xe) < 1270 && !IS_DGFX(xe); in xe_ttm_stolen_cpu_access_needs_ggtt()
60 static s64 detect_bar2_dgfx(struct xe_device *xe, struct xe_ttm_stolen_mgr *mgr) in detect_bar2_dgfx() argument
62 struct xe_tile *tile = xe_device_get_root_tile(xe); in detect_bar2_dgfx()
63 struct xe_gt *mmio = xe_root_mmio_gt(xe); in detect_bar2_dgfx()
64 struct pci_dev *pdev = to_pci_dev(xe->drm.dev); in detect_bar2_dgfx()
69 tile_offset = tile->mem.vram.io_start - xe->mem.vram.io_start; in detect_bar2_dgfx()
74 if (drm_WARN_ON(&xe->drm, tile_size < mgr->stolen_base)) in detect_bar2_dgfx()
75 return 0; in detect_bar2_dgfx()
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| D | xe_pci_sriov.c | 27 static int pf_provision_vfs(struct xe_device *xe, unsigned int num_vfs) in pf_provision_vfs() argument
31 int result = 0, err; in pf_provision_vfs()
33 for_each_gt(gt, xe, id) { in pf_provision_vfs()
43 static void pf_unprovision_vfs(struct xe_device *xe, unsigned int num_vfs) in pf_unprovision_vfs() argument
49 for_each_gt(gt, xe, id) in pf_unprovision_vfs()
54 static void pf_reset_vfs(struct xe_device *xe, unsigned int num_vfs) in pf_reset_vfs() argument
60 for_each_gt(gt, xe, id) in pf_reset_vfs()
65 static int pf_enable_vfs(struct xe_device *xe, int num_vfs) in pf_enable_vfs() argument
67 struct pci_dev *pdev = to_pci_dev(xe->drm.dev); in pf_enable_vfs()
68 int total_vfs = xe_sriov_pf_get_totalvfs(xe); in pf_enable_vfs()
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| D | xe_debugfs.c | 39 struct xe_device *xe = node_to_xe(m->private); in info() local
44 xe_pm_runtime_get(xe); in info()
46 drm_printf(&p, "graphics_verx100 %d\n", xe->info.graphics_verx100); in info()
47 drm_printf(&p, "media_verx100 %d\n", xe->info.media_verx100); in info()
49 xe_step_name(xe->info.step.graphics), in info()
50 xe_step_name(xe->info.step.media), in info()
51 xe_step_name(xe->info.step.basedie)); in info()
52 drm_printf(&p, "is_dgfx %s\n", str_yes_no(xe->info.is_dgfx)); in info()
53 drm_printf(&p, "platform %d\n", xe->info.platform); in info()
55 xe->info.subplatform > XE_SUBPLATFORM_NONE ? xe->info.subplatform : 0); in info()
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| D | xe_pci.c | 83 .rel = 0,
148 .has_flat_ccs = 0,
159 .has_flat_ccs = 0,
186 .rel = 0,
237 static const u16 adls_rpls_ids[] = { XE_RPLS_IDS(NOP), 0 };
252 static const u16 adlp_rplu_ids[] = { XE_RPLU_IDS(NOP), 0 };
289 static const u16 dg2_g10_ids[] = { XE_DG2_G10_IDS(NOP), XE_ATS_M150_IDS(NOP), 0 };
290 static const u16 dg2_g11_ids[] = { XE_DG2_G11_IDS(NOP), XE_ATS_M75_IDS(NOP), 0 };
291 static const u16 dg2_g12_ids[] = { XE_DG2_G12_IDS(NOP), 0 };
371 PCI_BASE_CLASS_DISPLAY << 16, 0xff << 16, \
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| D | xe_vram.c | 27 _resize_bar(struct xe_device *xe, int resno, resource_size_t size) in _resize_bar() argument
29 struct pci_dev *pdev = to_pci_dev(xe->drm.dev); in _resize_bar()
38 …drm_info(&xe->drm, "Failed to resize BAR%d to %dM (%pe). Consider enabling 'Resizable BAR' support… in _resize_bar()
43 drm_info(&xe->drm, "BAR%d resized to %dM\n", resno, 1 << bar_size); in _resize_bar()
50 static void resize_vram_bar(struct xe_device *xe) in resize_vram_bar() argument
53 struct pci_dev *pdev = to_pci_dev(xe->drm.dev); in resize_vram_bar()
78 drm_info(&xe->drm, in resize_vram_bar()
79 "Requested size: %lluMiB is not supported by rebar sizes: 0x%x. Leaving default: %lluMiB\n", in resize_vram_bar()
96 drm_info(&xe->drm, "Attempting to resize bar from %lluMiB -> %lluMiB\n", in resize_vram_bar()
104 (u64)root_res->start > 0x100000000ul) in resize_vram_bar()
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| D | xe_heci_gsc.c | 16 #define GSC_BAR_LENGTH 0x00000FFC
18 #define DG1_GSC_HECI2_BASE 0x259000
19 #define PVC_GSC_HECI2_BASE 0x285000
20 #define DG2_GSC_HECI2_BASE 0x374000
91 void xe_heci_gsc_fini(struct xe_device *xe) in xe_heci_gsc_fini() argument
93 struct xe_heci_gsc *heci_gsc = &xe->heci_gsc; in xe_heci_gsc_fini()
95 if (!HAS_HECI_GSCFI(xe) && !HAS_HECI_CSCFI(xe)) in xe_heci_gsc_fini()
106 if (heci_gsc->irq >= 0) in xe_heci_gsc_fini()
111 static int heci_gsc_irq_setup(struct xe_device *xe) in heci_gsc_irq_setup() argument
113 struct xe_heci_gsc *heci_gsc = &xe->heci_gsc; in heci_gsc_irq_setup()
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| D | xe_sriov.c | 36 static bool test_is_vf(struct xe_device *xe) in test_is_vf() argument
38 u32 value = xe_mmio_read32(xe_root_mmio_gt(xe), VF_CAP_REG); in test_is_vf()
45 * @xe: the &xe_device to probe mode on
54 void xe_sriov_probe_early(struct xe_device *xe) in xe_sriov_probe_early() argument
56 struct pci_dev *pdev = to_pci_dev(xe->drm.dev); in xe_sriov_probe_early()
58 bool has_sriov = xe->info.has_sriov; in xe_sriov_probe_early()
61 if (test_is_vf(xe)) in xe_sriov_probe_early()
63 else if (xe_sriov_pf_readiness(xe)) in xe_sriov_probe_early()
73 drm_info(&xe->drm, "Support for SR-IOV is not available\n"); in xe_sriov_probe_early()
74 pci_sriov_set_totalvfs(pdev, 0); in xe_sriov_probe_early()
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| D | xe_bo_evict.c | 16 * @xe: xe device
27 int xe_bo_evict_all(struct xe_device *xe) in xe_bo_evict_all() argument
29 struct ttm_device *bdev = &xe->ttm; in xe_bo_evict_all()
50 if (mem_type == XE_PL_TT && (IS_DGFX(xe) || !xe_device_has_flat_ccs(xe))) in xe_bo_evict_all()
62 spin_lock(&xe->pinned.lock); in xe_bo_evict_all()
64 bo = list_first_entry_or_null(&xe->pinned.external_vram, in xe_bo_evict_all()
70 spin_unlock(&xe->pinned.lock); in xe_bo_evict_all()
77 spin_lock(&xe->pinned.lock); in xe_bo_evict_all()
79 &xe->pinned.external_vram); in xe_bo_evict_all()
80 spin_unlock(&xe->pinned.lock); in xe_bo_evict_all()
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| D | xe_query.c | 43 static size_t calc_hw_engine_info_size(struct xe_device *xe) in calc_hw_engine_info_size() argument
49 int i = 0; in calc_hw_engine_info_size()
51 for_each_gt(gt, xe, gt_id) in calc_hw_engine_info_size()
94 u32 upper, lower, old_upper, loop = 0; in __read_timestamps()
110 query_engine_cycles(struct xe_device *xe, in query_engine_cycles() argument
121 if (query->size == 0) { in query_engine_cycles()
123 return 0; in query_engine_cycles()
124 } else if (XE_IOCTL_DBG(xe, query->size != size)) { in query_engine_cycles()
140 gt = xe_device_get_gt(xe, eci->gt_id); in query_engine_cycles()
165 if (GRAPHICS_VER(xe) >= 20) in query_engine_cycles()
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| D | xe_device.h | 32 static inline struct xe_device *xe_device_const_cast(const struct xe_device *xe) in xe_device_const_cast() argument
34 return (struct xe_device *)xe; in xe_device_const_cast()
44 int xe_device_probe_early(struct xe_device *xe);
45 int xe_device_probe(struct xe_device *xe);
46 void xe_device_remove(struct xe_device *xe);
47 void xe_device_shutdown(struct xe_device *xe);
49 void xe_device_wmb(struct xe_device *xe);
56 static inline struct xe_tile *xe_device_get_root_tile(struct xe_device *xe) in xe_device_get_root_tile() argument
58 return &xe->tiles[0]; in xe_device_get_root_tile()
66 gt_id = 0; in xe_tile_get_gt()
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| D | xe_rtp.c | 27 static bool has_samedia(const struct xe_device *xe) in has_samedia() argument
29 return xe->info.media_verx100 >= 1300; in has_samedia()
32 static bool rule_matches(const struct xe_device *xe, in rule_matches() argument
39 unsigned int i, rcount = 0; in rule_matches()
42 for (r = rules, i = 0; i < n_rules; r = &rules[++i]) { in rule_matches()
52 match = xe->info.platform == r->platform; in rule_matches()
55 match = xe->info.platform == r->platform && in rule_matches()
56 xe->info.subplatform == r->subplatform; in rule_matches()
59 match = xe->info.graphics_verx100 == r->ver_start && in rule_matches()
60 (!has_samedia(xe) || !xe_gt_is_media_type(gt)); in rule_matches()
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| D | xe_bo.c | 41 .fpfn = 0,
42 .lpfn = 0,
44 .flags = 0,
54 .fpfn = 0,
55 .lpfn = 0,
60 .fpfn = 0,
61 .lpfn = 0,
77 static bool resource_is_stolen_vram(struct xe_device *xe, struct ttm_resource *res) in resource_is_stolen_vram() argument
79 return res->mem_type == XE_PL_STOLEN && IS_DGFX(xe); in resource_is_stolen_vram()
133 mem_type_to_migrate(struct xe_device *xe, u32 mem_type) in mem_type_to_migrate() argument
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| D | xe_exec_queue.c | 28 XE_EXEC_QUEUE_JOB_TIMEOUT = 0,
34 static int exec_queue_user_extensions(struct xe_device *xe, struct xe_exec_queue *q,
48 static struct xe_exec_queue *__xe_exec_queue_alloc(struct xe_device *xe, in __xe_exec_queue_alloc() argument
98 err = exec_queue_user_extensions(xe, q, extensions, 0); in __xe_exec_queue_alloc()
119 for (i = 0; i < q->width; ++i) { in __xe_exec_queue_init()
134 return 0; in __xe_exec_queue_init()
140 for (i = i - 1; i >= 0; --i) in __xe_exec_queue_init()
145 struct xe_exec_queue *xe_exec_queue_create(struct xe_device *xe, struct xe_vm *vm, in xe_exec_queue_create() argument
153 q = __xe_exec_queue_alloc(xe, vm, logical_mask, width, hwe, flags, in xe_exec_queue_create()
169 struct xe_exec_queue *xe_exec_queue_create_class(struct xe_device *xe, struct xe_gt *gt, in xe_exec_queue_create_class() argument
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| D | xe_sriov_pf.c | 15 static unsigned int wanted_max_vfs(struct xe_device *xe) in wanted_max_vfs() argument
20 static int pf_reduce_totalvfs(struct xe_device *xe, int limit) in pf_reduce_totalvfs() argument
22 struct device *dev = xe->drm.dev; in pf_reduce_totalvfs()
28 xe_sriov_notice(xe, "Failed to set number of VFs to %d (%pe)\n", in pf_reduce_totalvfs()
33 static bool pf_continue_as_native(struct xe_device *xe, const char *why) in pf_continue_as_native() argument
35 xe_sriov_dbg(xe, "%s, continuing as native\n", why); in pf_continue_as_native()
36 pf_reduce_totalvfs(xe, 0); in pf_continue_as_native()
42 * @xe: the &xe_device to check
49 bool xe_sriov_pf_readiness(struct xe_device *xe) in xe_sriov_pf_readiness() argument
51 struct device *dev = xe->drm.dev; in xe_sriov_pf_readiness()
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| D | xe_hwmon.c | 62 * struct xe_hwmon - xe hwmon data structure
65 /** @hwmon_dev: hwmon device for xe */
67 /** @xe: Xe device */
68 struct xe_device *xe; member
84 struct xe_device *xe = hwmon->xe; in xe_hwmon_get_reg() local
88 if (xe->info.platform == XE_BATTLEMAGE) { in xe_hwmon_get_reg()
93 } else if (xe->info.platform == XE_PVC && channel == CHANNEL_PKG) { in xe_hwmon_get_reg()
95 } else if ((xe->info.platform == XE_DG2) && (channel == CHANNEL_PKG)) { in xe_hwmon_get_reg()
100 if (xe->info.platform == XE_BATTLEMAGE) in xe_hwmon_get_reg()
102 else if (xe->info.platform == XE_PVC && channel == CHANNEL_PKG) in xe_hwmon_get_reg()
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| /linux-6.12.1/drivers/gpu/drm/xe/display/ |
| D | xe_display.c | 33 /* Xe device functions */
35 static bool has_display(struct xe_device *xe) in has_display() argument
37 return HAS_DISPLAY(xe); in has_display()
50 return 0; in xe_display_driver_probe_defer()
71 static void unset_display_features(struct xe_device *xe) in unset_display_features() argument
73 xe->drm.driver_features &= ~(DRIVER_MODESET | DRIVER_ATOMIC); in unset_display_features()
78 struct xe_device *xe = to_xe_device(dev); in display_destroy() local
80 destroy_workqueue(xe->display.hotplug.dp_wq); in display_destroy()
85 * @xe: XE device instance
90 * to the rest of xe and return it to be xe->display.
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| D | xe_display.h | 17 void xe_display_driver_remove(struct xe_device *xe);
19 int xe_display_create(struct xe_device *xe);
21 int xe_display_probe(struct xe_device *xe);
23 int xe_display_init_nommio(struct xe_device *xe);
24 int xe_display_init_noirq(struct xe_device *xe);
25 int xe_display_init_noaccel(struct xe_device *xe);
26 int xe_display_init(struct xe_device *xe);
27 void xe_display_fini(struct xe_device *xe);
29 void xe_display_register(struct xe_device *xe);
30 void xe_display_unregister(struct xe_device *xe);
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| D | xe_hdcp_gsc.c | 33 bool intel_hdcp_gsc_cs_required(struct xe_device *xe) in intel_hdcp_gsc_cs_required() argument
35 return DISPLAY_VER(xe) >= 14; in intel_hdcp_gsc_cs_required()
38 bool intel_hdcp_gsc_check_status(struct xe_device *xe) in intel_hdcp_gsc_check_status() argument
40 struct xe_tile *tile = xe_device_get_root_tile(xe); in intel_hdcp_gsc_check_status()
46 drm_dbg_kms(&xe->drm, in intel_hdcp_gsc_check_status()
51 xe_pm_runtime_get(xe); in intel_hdcp_gsc_check_status()
53 drm_dbg_kms(&xe->drm, in intel_hdcp_gsc_check_status()
64 xe_pm_runtime_put(xe); in intel_hdcp_gsc_check_status()
69 static int intel_hdcp_gsc_initialize_message(struct xe_device *xe, in intel_hdcp_gsc_initialize_message() argument
74 int ret = 0; in intel_hdcp_gsc_initialize_message()
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| /linux-6.12.1/drivers/gpu/drm/xe/compat-i915-headers/ |
| D | i915_drv.h | 9 * "Adaptation header" to allow i915 display to also build for xe driver.
10 * TODO: refactor i915 and xe so this can cease to exist
24 #define IS_PLATFORM(xe, x) ((xe)->info.platform == x) argument
26 #define IS_I830(dev_priv) (dev_priv && 0)
27 #define IS_I845G(dev_priv) (dev_priv && 0)
28 #define IS_I85X(dev_priv) (dev_priv && 0)
29 #define IS_I865G(dev_priv) (dev_priv && 0)
30 #define IS_I915G(dev_priv) (dev_priv && 0)
31 #define IS_I915GM(dev_priv) (dev_priv && 0)
32 #define IS_I945G(dev_priv) (dev_priv && 0)
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| /linux-6.12.1/drivers/gpu/drm/xe/tests/ |
| D | xe_migrate.c | 15 static bool sanity_fence_failed(struct xe_device *xe, struct dma_fence *fence, in sanity_fence_failed() argument
29 if (ret <= 0) { in sanity_fence_failed()
37 static int run_sanity_job(struct xe_migrate *m, struct xe_device *xe, in run_sanity_job() argument
41 u64 batch_base = xe_migrate_batch_base(m, xe->info.has_usm); in run_sanity_job()
57 if (sanity_fence_failed(xe, fence, str, test)) in run_sanity_job()
62 return 0; in run_sanity_job()
70 } } while (0)
75 struct xe_device *xe = tile_to_xe(m->tile); in test_copy() local
76 u64 retval, expected = 0; in test_copy()
82 struct xe_bo *remote = xe_bo_create_locked(xe, m->tile, NULL, in test_copy()
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| /linux-6.12.1/Documentation/ABI/testing/ |
| D | sysfs-driver-intel-xe-hwmon | 1 What: /sys/bus/pci/drivers/xe/.../hwmon/hwmon<i>/power1_max
4 Contact: intel-xe@lists.freedesktop.org
9 exceeds this limit. A read value of 0 means that the PL1
10 power limit is disabled, writing 0 disables the
11 limit. Writing values > 0 and <= TDP will enable the power limit.
13 Only supported for particular Intel Xe graphics platforms.
15 What: /sys/bus/pci/drivers/xe/.../hwmon/hwmon<i>/power1_rated_max
18 Contact: intel-xe@lists.freedesktop.org
21 Only supported for particular Intel Xe graphics platforms.
24 What: /sys/bus/pci/drivers/xe/.../hwmon/hwmon<i>/energy1_input
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